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Berkeley ELENG 42 - Data Transfer

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PowerPoint PresentationData transferMultiplexer vs tri-state/busMultiplexerBus with tri-state driversBusSynchronous v. AsynchronousSynchronousAsynchronous circuitasynchronousMetastability and Asynchronous inputsSynchronous communicationHandling Asynchronous Inputs (cont’d)Synchronization FailureDealing with Synchronization FailureEdge-Triggered Flip-FlopsDefinition: Set up time/hold timeHandling Asynchronous InputsAsynchronous LogicKey Design DifferencesDifficulties with asynchronous designClock skewSerial transmissionLong signal pathsGate delaySlide 26Light speedTransmission LineSlide 29Slide 30Transmission line impedanceTransmission line termination11/19/2004 EE 42 fall 2004 lecture 34 1Lecture #34: data transfer•Last lecture:–Example circuits–shift registers–Adders–Counters•This lecture–Communications synchronous / asynchronous –Buses–Start transmission lines11/19/2004 EE 42 fall 2004 lecture 34 2Data transfer•In addition to computation, it is necessary to transmit information from one place to another.•Buses are used to move data from one logic device to another in parallel•If the devices are close together, the delay is the RC time to charge the capacitance.•If the devices are further apart, need to consider propagation velocity, distortion, crosstalk.11/19/2004 EE 42 fall 2004 lecture 34 3Multiplexer vs tri-state/bus•To send information to several different destinations, you can just run wires to each of the destinations.•But to have information from several sources go to the same destination, you need to control which device drives the destination, can not tolerate pulling up and down on the same wire.•This can be done using multiplexers, or by using tri-state drivers in a bus architecture11/19/2004 EE 42 fall 2004 lecture 34 4MultiplexerFor example, if you have four inputs, you would need a 2 selector 4 input multiplexer for each bit of output.I1I2I3I42 input decoderABO11/19/2004 EE 42 fall 2004 lecture 34 5Bus with tri-state drivers•To efficiently route information from many source, a bus can be driven by tri-state drivers. The logic must ensure that only one driver is active at a time.11/19/2004 EE 42 fall 2004 lecture 34 6Bus•A bus may be synchronous, to a clock edge for example, or asynchronous with handshaking and control linesData 0Data 1Data 2Data 3Data 4Data 5Data 6Data 7Clock11/19/2004 EE 42 fall 2004 lecture 34 7Synchronous v. AsynchronousClock SignalHandshake ControlAsynchronous CircuitSynchronous Circuit11/19/2004 EE 42 fall 2004 lecture 34 8Synchronous•In a synchronous circuit, there is an explicit global synchronization through the clock signal.•The clock period is chosen to be longer than the worst case delay (gate delays + transmission delays)11/19/2004 EE 42 fall 2004 lecture 34 9Asynchronous circuitR R R RReqAckSynchronization with Req / Ack handshakesLogicLogicLogic11/19/2004 EE 42 fall 2004 lecture 34 10asynchronous•Asynchronous design is often unavoidable:–User interfaces–Different speed devices–Clocks are difficult to distribute over long distances•More difficult to design, design tools generally have been synchronous only, but asynchronous design tools are being developed.•Most current devices us synchronous logic inside local blocks, and asynchronous communication between blocks.•What constitutes a “block” is shrinking as logic speeds increase.–Currently making jump to chips with multiple independent blocks, or fully asynchronous logic.11/19/2004 EE 42 fall 2004 lecture 34 11Metastability and Asynchronous inputs•Clocked synchronous circuits–Inputs, state, and outputs sampled or changed in relation to acommon reference signal (called the clock)–E.g., master/slave, edge-triggered•Asynchronous circuits–Inputs, state, and outputs sampled or changed independently of a common reference signal (glitches/hazards a major concern)–E.g., R-S latch•Asynchronous inputs to synchronous circuits–Inputs can change at any time, will not meet setup/hold times–Dangerous, synchronous inputs are greatly preferred–Cannot be avoided (e.g., reset signal, memory wait, user input)11/19/2004 EE 42 fall 2004 lecture 34 12Synchronous communication•Clock edges determine the time instants where data must be sampled•Data wires may glitch between clock edges(data must be stable for set–up/hold times)1 1 0 0 1 011/19/2004 EE 42 fall 2004 lecture 34 13In is asynchronous and fans out to D0 and D1one FF catches the signal, one does notState of Q0 and Q1 is inconsistentInQ0Q1CLKHandling Asynchronous Inputs (cont’d)•What can go wrong?–Input changes too close to clock edge (violating setup time constraint)11/19/2004 EE 42 fall 2004 lecture 34 14 small, but non-zero probability that the FF output will get stuck in an in-between stateoscilloscope traces demonstratingsynchronizer failure and eventualdecay to steady statelogic 0logic 1logic 0logic 1Synchronization Failure•Occurs when FF input changes close to clock edge–FF may enter a metastable state – neither a logic 0 nor 1 ––May stay in this state an indefinite amount of time–Is not likely in practice but has some probability11/19/2004 EE 42 fall 2004 lecture 34 15DDQQasynchronousinputsynchronizedinputsynchronous systemClkDealing with Synchronization Failure•Probability of failure can never be reduced to 0, but it can be reduced–(1) slow down the system clock: this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems–(2) use fastest possible logic technology in the synchronizer:this makes for a very sharp "peak" upon which to balance–(3) cascade two synchronizers: this effectively synchronizes twice (both would have to fail)11/19/2004 EE 42 fall 2004 lecture 34 16QDClk=1RSQ’negative edge-triggered D flip-flop (D-FF)4-5 gate delaysmust respect setup and hold time constraints to successfullycapture inputcharacteristic equationQ(t+1) = Dholds D' whenclock goes lowholds D whenclock goes lowEdge-Triggered Flip-Flops•More efficient solution: only 6 gates–sensitive to inputs only near edge of clock signal (not while high)11/19/2004 EE 42 fall 2004 lecture 34 17clockdatachangingstableinputclockTsuThclockdataD Q D QDefinition: Set up time/hold timeTo ensure that the data signal is captured accurately, the data must be stable for an time tsu (set up) before the edge, and kept constant for a time th (hold) after the edge.11/19/2004 EE 42 fall


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Berkeley ELENG 42 - Data Transfer

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Lecture 1

Lecture 1

25 pages

Lecture 2

Lecture 2

20 pages

Lecture 3

Lecture 3

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Midterm 1

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