PowerPoint PresentationDRAM OperationsDRAM logical organizationDRAM sense ampDRAM sense amplifierDRAM/SRAM tradeoffsNonvolatile memoryTrapped chargeUV Erase PROMUV EPROMElectrical EPROMEEPromProgramming/erasingEEPROMFlashMemory Comparison gridFlash Memory ComparisonAdvanced memory technologiesFRAMFerroelectric materialTunneling Magnetic Junction12/1/2004 EE 42 fall 2004 lecture 38 1Lecture #38: Memory (2)•Last lecture:–Memory Architecture–Static Ram•This lecture–Dynamic Ram–E2 memory12/1/2004 EE 42 fall 2004 lecture 38 2DRAM Operations•Write–Charge bitline HIGH or LOW and set wordline HIGH•Read–Bit line is precharged to a voltage halfway between HIGH and LOW, and then the word line is set HIGH. –Depending on the charge in the cap, the precharged bitline is pulled slightly higheror lower.–Sense Amp Detects change•The signal is decreased by the ratio of the storage capacitance to the bitline capacitance–Increase density => increase parasiticcapacitance–As geometries shrink, still need large bit capacitanceWord LineBit LineCSense Amp...12/1/2004 EE 42 fall 2004 lecture 38 3DRAM logical organization Column DecoderSense Amps & I/OMemory ArrayA0…A10…11DQ…Row decoderSelectWrite enableControl logic12/1/2004 EE 42 fall 2004 lecture 38 4DRAM sense ampenableenableenableenableBit lineBoth precharged to ½ V Data out+V12/1/2004 EE 42 fall 2004 lecture 38 5DRAM sense amplifier•The reason that DRAM is slow, is that a very small charge is captured on the capacitor, and the small voltage change on the line must be sensed. timeVPrecharge→Charge dumped to bit lineSense amp decides 0 or 112/1/2004 EE 42 fall 2004 lecture 38 6DRAM/SRAM tradeoffs•By it’s nature, DRAM isn’t built for speed–Response time dependent on capacitive circuit properties which get worse as density increases•DRAM process isn’t easy to integrate into CMOS process–DRAM is off chip –Connectors, wires, etc introduce slowness–IRAM efforts looking to integrating the two•Memory Architectures are designed to minimize impact of DRAM latency–Use dram for high density, store data which is used often in smaller, higher speed SRAM cache.12/1/2004 EE 42 fall 2004 lecture 38 7Nonvolatile memory•One disadvantage of both SRAM and DRAM is that if power is removed, the contents is lost.•One solution is to use SRAM designed to use very little current, and then to maintain power with a battery•Another solution is to use a memory type which physically alters the cell, such as EE memory12/1/2004 EE 42 fall 2004 lecture 38 8Trapped charge•Most current nonvolatile memories use a modified MOSFET with a floating gate•The floating gate can be charged or discharged by electrons moving through the oxide.•In the oldest technology, the EPROM, the floating gate is charged by hot electrons tunneling through a thin oxide, but can only be discharged by ultraviolet light exposure to the whole chip12/1/2004 EE 42 fall 2004 lecture 38UV Erase PROM nSourceDrainThin Oxide+n+p-SubstrateSiO2SiO2Control Gate Floating Gate12/1/2004 EE 42 fall 2004 lecture 38+++++++++++UV EPROMn+ n+ProgramVss VddVggn+ n+Erase------------------UV LightHot electrons12/1/2004 EE 42 fall 2004 lecture 38Electrical EPROMn+ n+Control GateStorage Gate12/1/2004 EE 42 fall 2004 lecture 38 12EEProm•In an EEPROM, (electrically erasable) the electrons can be tunneled back off the floating gate by applying a high voltage between the control gate and the source12/1/2004 EE 42 fall 2004 lecture 38 13Programming/erasing•The floating gate programmed by running a current of electrons from the source to the drain, then placing a large voltage on the control gate, a strong enough electric field to let them go through the oxide to the floating gate, a process called hot-electron injection. •To erase a flash cell, a large voltage differential is placed between the control gate and source, which pulls the electrons off the floating gate through Fowler-Nordheim tunneling, a quantum mechanical tunneling process.12/1/2004 EE 42 fall 2004 lecture 38EEPROM n+ n+ n+ n+VssVdd++++++++eee- - - - - - - - - -VssVdd+++ eeeHot electrons12/1/2004 EE 42 fall 2004 lecture 38 15Flash• Flash memory can be erased and reprogrammed in units of memory called blocks. It is a form of EERAM, which, unlike flash memory, is erased and rewritten at the byte level.•Erasing and rewriting as a block means faster writing times for large blocks of data. •Flash memory gets its name because the microchip is organized so that a section of memory cells are erased in a single action or "flash." •The erasure is caused by Fowler-Nordheim tunneling in which electrons go through a thin oxide to remove an electronic charge from the floating gate.12/1/2004 EE 42 fall 2004 lecture 38Memory Comparison gridMemory typeRead speedWrite speedVolatility density power rewriteSRAM +++ +++ - - ++DRAM + + - - ++ - ++EPROM + - + + -EEPROM + - + + +Flash + + + + +12/1/2004 EE 42 fall 2004 lecture 38Flash Memory Comparison•FLASH cells can be roughly made two or three times smaller than the EEPROM•Flash memory allows faster and more frequent programming than EPROM•Flash memory provides better data reliability than battery-backed SRAM•Flash memory fits in applications that might otherwise have used ROM (EEPROM), battery-backed RAM, or magnetic mass storage12/1/2004 EE 42 fall 2004 lecture 38Advanced memory technologies•Ferroelectric Random Access Memory (FRAMs)•Magnetoresistive Random Access Memories (MRAMs)•Experimental Memories–Quantum-Mechanical Switch Memories–Single Electron Memory•Tunneling Magnetic Junction RAM (TMJ-RAM):–Speed of SRAM, density of DRAM, non-volatile (no refresh)–“Spintronics” electron spin effects transport–Same technology used in the read heads of high-density disk-drives: Giant magneto-resistive effect12/1/2004 EE 42 fall 2004 lecture 38 19FRAM12/1/2004 EE 42 fall 2004 lecture 38 20Ferroelectric material12/1/2004 EE 42 fall 2004 lecture 38 21Tunneling Magnetic
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