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Berkeley ELENG 42 - Fabrication

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Week 14 FabricationPowerPoint PresentationMOSFET Layout and Cross-SectionSlide 4Computing the Output CapacitanceSlide 6Si Substrates (Wafers)Adding Dopants into SiDopant DiffusionFormation of Insulating FilmsThermal OxidationExample: Thermal Oxidation of SiliconEffect of Oxidation Rate Dependence on ThicknessSelective Oxidation TechniquesChemical Vapor Deposition (CVD) of SiO2Chemical Vapor Deposition (CVD) of SiPhysical Vapor Deposition (“Sputtering”)Patterning the LayersThe Photo-Lithographic ProcessPhotoresist ExposureExposure using “Stepper” ToolPhotoresist DevelopmentLithography Example“A-A” Cross-Section“B-B” Cross-SectionPattern Transfer by EtchingPhotolithographyLithography TrendsPlasma ProcessingDry Etching vs. Wet EtchingSlide 31Rapid Thermal Annealing (RTA)Chemical Mechanical Polishing (CMP)Copper MetallizationCMP ToolWeek 14, Slide 1EECS 42, Spring 2005 Prof. WhiteWeek 14 FabricationOUTLINE•IC Fabrication Technology–Introduction – the task at hand–Doping–Oxidation–Thin-film deposition–Lithography–Etch–Lithography trends–Plasma processing–Chemical mechanical polishingReading (Rabaey et al.)•Sections 2.1-2.2Week 14, Slide 2EECS 42, Spring 2005 Prof. White1972 3,5001974 6,0001978 29,0001982 134,0001985 275,0001989 1,200,0001993 3,100,0001995 5,500,0001997 7,500,0001999 19,000,000Year Transistors Per Chip2000 28,100,000Moore’s Law – Increasing Number of Transistors on a ChipTransistor count vs. year on Intel computer chipsTransistors on a ChipYearNumber of transistors per chip doubles every 18 to 24 monthsWeek 14, Slide 3EECS 42, Spring 2005 Prof. WhiteMOSFET Layout and Cross-SectionTop View:Cross Section:Week 14, Slide 4EECS 42, Spring 2005 Prof. WhiteN-channel MOSFETSchematic Cross-Sectional ViewLayout (Top View)4 lithography steps are required: 1. active area 2. gate electrode 3. contact 4. metal interconnectsWeek 14, Slide 5EECS 42, Spring 2005 Prof. WhiteComputing the Output CapacitanceInOutMetal1VDDGNDPoly-Si PMOSW/L=9/2InOutExample 5.4 (pp. 197-203) NMOSW/L=3/2 2=0.25mWeek 14, Slide 6EECS 42, Spring 2005 Prof. WhiteIntegrated Circuit FabricationGoal: Mass fabrication (i.e. simultaneous fabrication) of many “chips”, each a circuit (e.g. a microprocessor or memory chip) containing millions or billions of transistorsMethod:Lay down thin films of semiconductors, metals and insulators and pattern each layer with a process much like printing (lithography).Materials used in a basic CMOS integrated circuit:• Si substrate – selectively doped in various regions• SiO2 insulator• Polycrystalline silicon – used for the gate electrodes• Metal contacts and wiringWeek 14, Slide 7EECS 42, Spring 2005 Prof. WhiteSi Substrates (Wafers)Crystals are grown from a melt in boules (cylinders) with specified dopant concentrations. They are ground perfectly round and oriented (a “flat” or “notch” is ground along the boule) and then sliced like baloney into wafers. The wafers are then polished. Typical wafer cost: $50Sizes: 150 mm, 200 mm, 300 mm diameter300 mm“notch” indicatescrystal orientationWeek 14, Slide 8EECS 42, Spring 2005 Prof. WhiteSuppose we have a wafer of Si which is p-type and we want to change the surface to n-type. The way in which this is done is by ion implantation. Dopant ions are shot out of an “ion gun” called an ion implanter, into the surface of the wafer. Typical implant energies are in the range 1-200 keV. After the ion implantation, the wafers are heated to a high temperature (~1000oC). This “annealing” step heals the damage and causes the implanted dopant atoms to move into substitutional lattice sites.Adding Dopants into SiEaton HE3High-Energy Implanter,showing the ion beam hitting theend-stationWeek 14, Slide 9EECS 42, Spring 2005 Prof. White•The implanted depth-profile of dopant atoms is peaked.•In order to achieve a more uniform dopant profile, high-temperature annealing is used to diffuse the dopants•Dopants can also be directly introduced into the surface of a wafer by diffusion (rather than by ion implantation) from a dopant-containing ambient or doped solid sourceDopant Diffusiondopant atomconcentration(logarithmic scale)as-implanted profiledepth, xWeek 14, Slide 10EECS 42, Spring 2005 Prof. White•The favored insulator is pure silicon dioxide (SiO2).•A SiO2 film can be formed by one of two methods:1. Oxidation of Si at high temperature in O2 or steam ambient2. Deposition of a silicon dioxide filmFormation of Insulating FilmsASM A412batchoxidationfurnaceApplied Materials low-pressure chemical-vapor deposition (CVD) chamberWeek 14, Slide 11EECS 42, Spring 2005 Prof. White22SiOOSi Thermal Oxidation•Temperature range:700oC to 1100oC•Process: O2 or H2O diffuses through SiO2 and reacts with Si at the interface to form more SiO2•1 m of SiO2 formed consumes ~0.5 m of Sioxidethicknesstttime, t22222 HSiOOHSi or“dry” oxidation“wet” oxidationWeek 14, Slide 12EECS 42, Spring 2005 Prof. WhiteThermal oxidation grows SiO2 on Si, but it consumes Si, so the wafer gets thinner. Suppose we grow 1 m of oxide:Silicon wafer, 100 m thickExample: Thermal Oxidation of Silicon99 m thick Si, with 1 m SiO2 all around  total thickness = 101 m99m101mWeek 14, Slide 13EECS 42, Spring 2005 Prof. White•The thermal oxidation rate slows with oxide thickness.Consider a Si wafer with a patterned oxide layer:Now suppose we grow 0.1 m of SiO2:SiO2 thickness = 1 mSiO2 thickness = 1.02 mSiO2 thickness = 0.1 mSiEffect of Oxidation Rate Dependence on ThicknessNote the 0.04m step in the Si surface!Week 14, Slide 14EECS 42, Spring 2005 Prof. WhiteLocal Oxidation (LOCOS)Window OxidationSelective Oxidation TechniquesWeek 14, Slide 15EECS 42, Spring 2005 Prof. WhiteChemical Vapor Deposition (CVD) of SiO222242HSiOOSiH •Temperature range:350oC to 450oC for silane•Process: Precursor gases dissociate at the wafer surface to form SiO2No Si on the wafer surface is consumed•Film thickness is controlled by the deposition timeoxidethicknessttime, t“LTO”Week 14, Slide 16EECS 42, Spring 2005 Prof. WhitePolycrystalline silicon (“poly-Si”):Like SiO2, Si can be deposited by Chemical Vapor Deposition:• Wafer is heated to ~600oC• Silicon-containing gas (SiH4) is injected into the furnace:SiH4 = Si + 2H2Properties:• sheet resistance (heavily doped, 0.5 m


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Berkeley ELENG 42 - Fabrication

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Lecture 3

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