Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 23: 11/26/01 A.R. NeureutherVersion Date 12/02/01P-MOS Device and CMOS InvertersA) P-MOS Device Structure and OperationB) Relation of Current to tOX, µ VLIMITC) CMOS Device Equations and UseD) CMOS Inverter VOUTvs. VINE) CMOS Short Circuit CurrentReading: Schwarz and Oldham, pp. 518-526Lecture 23Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 23: 11/26/01 A.R. NeureutherVersion Date 12/02/01CMOS = Complementary MOS(PMOS is a second Flavor)nPoxide insulatorndrainsourceN-MOSIn this device the gate controls electron flow from source to drain.The NEW FLAVOR! P-MOSIt is made in p-type silicon.It is made in n-type silicon.sourcedrainn-type Si P-MOSgateIn this device the gate controls hole flow from source to drain.gatep pCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 23: 11/26/01 A.R. NeureutherVersion Date 12/02/01PMOSIt is made in n-type silicon.In this device the gate controls hole flow from source to drain.sourcedrainn-type Si pgate+ -pWhat if we apply a big negative voltage on the gate? If |VGS|>|Vt | (both negative)then we induce a + charge on the surface (holes)sourcedrainn-type Si P-MOSgatep p|VGS|>|Vt |Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 23: 11/26/01 A.R. NeureutherVersion Date 12/02/01NMOS and PMOS ComparedNMOS“Body” – p-typeSource – n-typeDrain – n-type VGS– positive VT– positive VDS– positive ID– positive (into drain)PMOS“Body” – n-typeSource – p-typeDrain – p-type VGS– negative VT– negative VDS– negative ID– negative (into drain)GnnIDDSpBGp pIDDSnBID4321VDSVGS=3V1 mAVGS=0(for IDS= 1mA)4321−VDSVGS= −3V1 mAVGS=0−ID(for IDS= -1mA)Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 23: 11/26/01 A.R. NeureutherVersion Date 12/02/01CMOSChallenge: build both NMOS and PMOS on a single silicon chipNMOS needs a p-type substratePMOS needs an n-type substrateRequires extra process stepsoxideP-Si n-wellp p n nGDGDSSCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 23: 11/26/01 A.R. NeureutherVersion Date 12/02/01Why do we want PMOS?• A PMOS transistor is just the ticket. It is precisely as ideal a switch for connections to high as NMOS transistors are for connections to low.• What’s cool is that there is little more to learn about PMOS. These devices are essentially the same as NMOS except all signs on V and I are reversed.We already have the ideal switch to connect any node to ground.An NMOS transistor with gate held high has a very low resistance and essentially switches a node to ground (logic low).outputinput inputoutputVDDWe also need a switch to switch nodes to whatever voltage is chosen as logic high (typically VDD).Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 23: 11/26/01 A.R. NeureutherVersion Date 12/02/01THE BASIC STATIC CMOS INVERTERvoutvinVDDPMOSNMOSFor Vin< 1V NMOS off , PMOS onFor Vin> 1.5V NMOS on , PMOS offsourcedrainsourcedrainExample for Discussion: NMOS: VTn= 1VPMOS: VTp= -1VLet VDD= 2.5VVout = 0Vout = VDDVinVoutVDDVinVDDVoutCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 23: 11/26/01 A.R. NeureutherVersion Date 12/02/01MOS Current LevelsThe current values depend on the properties of silicon, geometrical layout, design style and technology node.n-type silicon has a carrier mobility that is 2 to 3 times higher than p-type.The current proportion to the gate width/length in the geometrical layout.Design styles may restrict all NMOS and PMOS to be of a predetermined fixed size.The current per unit width of the gate increases nearly inversely with the linewidth.Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 23: 11/26/01 A.R. NeureutherVersion Date 12/02/01Relation of Current to Physical ParametersnSATOUTTGSnoxnDVVVLWCI−−⋅−=)(µ()()27714/1075.51069.3/1085.8cmFxcmxcmFxtCoxoxox−−−==ε=Mobility of carriersOxide thicknessGeometrical LayoutExcess Gate driveVoltage of scattering velocity limit()Vscmn/5002=µ()Vscmp/1502=µ()VcmxcmVLEVCritnSATOUT25.01025.0/1044=⋅=⋅=−−−Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 23: 11/26/01 A.R. NeureutherVersion Date 12/02/01CMOS Device Parameters at 0.25µm2510.4PMOS1000.630.43NMOSk’ (µA/V2)VOUT-SAT (V)VT(V)Gate length is 0.25 µm = 250 nmVDD= 2.5V()AVVVVAIDSATOUTµµ196)63.0)(43.05.2)(25.0375.0(/1002=−=−−These parameters are from re-fitting I vs. V data in Chapter 3 of the EECS 141 Text Book by Rabaey with saturation current model we are using in EE42.()DSATOUTTDINDDSATOUTVVVkI−−−−−=Here VIN= VDDis used to estimate the maximum IDSCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 23: 11/26/01 A.R. NeureutherVersion Date 12/02/01Saturation Current 0.25 µm NMOS ModelCurrent IOUTonly flows when VINis larger than the threshold value VTDand the current is proportional to VOUTup to VOUT-SAT-nwhere it reaches the saturation current()nSATOUTTnINnnnSATOUTVVVLWkI−−−−−='()AVVVVAInµµ5.7763.04.025.125.0375.01002=−=Note that we have added an extra parameter to distinguish between threshold (VTD) and saturation (VOUT-SAT-D).VOUT(V)IOUT(µA)032.52060100VIN= 1.25VLinear (with VOUT)Saturation (with VOUT)Example:kn= 100 µA/V2VTn= 0.43VVOUT-SAT-n= 0.63VW = 0.375µmVDD= 2.5VHere VDD/2 is used to estimate the short-circuit currentCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 23: 11/26/01 A.R. NeureutherVersion Date 12/02/01Saturation Current 0.25 µm PMOS ModelCurrent IOUTonly flows when VINis smaller than VDD minus the threshold value VTUand the current is proportional to (VDD-VOUT) up to (VDD-VOUT-SAT-p) where it reaches the saturation current()pSATOUTTpINDDpppSATOUTVVVVLWkI−−−−−−='()AVVVVVAIpµµ8.6314.025.15.225.075.0252=−−=Saturation (with VOUT)VOUT(V)IOUT(µA)032.52060100VIN=
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