1Copyright 2003 , Regents of University of CaliforniaLecture 23: 11/18/03 A.R. NeureutherVersion Date 11/05/03EECS 42 Intro. Digital Electronics Fall 2003EECS 42 Introduction Digital ElectronicsAndrew R. NeureutherLecture # 22 Latches and PipeliningHandout of This Lecture. A) Timing Diagram for a Clocked LatchB) PipeliningC) Latency and Throughputhttp://inst.EECS.Berkeley.EDU/~ee42/Copyright 2003 , Regents of University of CaliforniaLecture 23: 11/18/03 A.R. NeureutherVersion Date 11/05/03EECS 42 Intro. Digital Electronics Fall 2003Latch Work Best In PairsThe second stage operates while the clock is high and inverts the signal on CL1to charge or discharge CL2and downstream logic gate inputs.VDDVOUT_EXTVDDVOUT_INTφφφφCL1CL2VINThe first stage operates while the clock is low and inverts and amplifies the arriving signal and charges or discharges CL1.timeClock102Copyright 2003 , Regents of University of CaliforniaLecture 23: 11/18/03 A.R. NeureutherVersion Date 11/05/03EECS 42 Intro. Digital Electronics Fall 2003Example of Circuits to Integrate with LatchesA1B1A1VDDVOUT-C2Gate 1CG1B1A2B2C2A2C1B2VDDVOUT-C1Gate 2CG2A3A3VDDVOUT_3D3B3C3B3C3D3DDSSCL3Gate 3τHL= 3τINVτLH= 3τINVτPD_CASCADE= τPD_1+ τPD_2Copyright 2003 , Regents of University of CaliforniaLecture 23: 11/18/03 A.R. NeureutherVersion Date 11/05/03EECS 42 Intro. Digital Electronics Fall 2003Logic Worst Case DelaysA1B1A1VDDVOUT-C2Gate 1CG1B1A2B2C2A2C1B2VDDVOUT-C1Gate 2CG2A3A3VDDVOUT_3D3B3C3B3C3D3DDSSCL3Gate 3τLH= 2τINVτHL= 2τINVτLH= 2τINVτHL= 3τINVτLH= 3τINV3Copyright 2003 , Regents of University of CaliforniaLecture 23: 11/18/03 A.R. NeureutherVersion Date 11/05/03EECS 42 Intro. Digital Electronics Fall 2003Latch Implementation: LumpedA1B1A1VDDVOUT-C2Gate 1CG1B1A2B2C2A2C1B2VDDVOUT-C1Gate 2CG2VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0Latch 0Latch 1Copyright 2003 , Regents of University of CaliforniaLecture 23: 11/18/03 A.R. NeureutherVersion Date 11/05/03EECS 42 Intro. Digital Electronics Fall 2003Latch Operation: LumpedA1B1A1VDDVOUT-C2CG1B1A2B2C2A2C1B2VDDVOUT-C1CG2VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0Latch 0Latch 1timeClock10LowLowHighHighGate 1Gate 2τHIGH= τL_EXT+ τGATE1+ τGATE2τLOW= τL_INT4Copyright 2003 , Regents of University of CaliforniaLecture 23: 11/18/03 A.R. NeureutherVersion Date 11/05/03EECS 42 Intro. Digital Electronics Fall 2003Latch Implementation: PipelinedLatch 1VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0Latch 0VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0Latch 2A2B2C2A2C1B2VDDVOUT-C1CG2Gate 2A1B1A1VDDVOUT-C2CG1B1Gate 1Copyright 2003 , Regents of University of CaliforniaLecture 23: 11/18/03 A.R. NeureutherVersion Date 11/05/03EECS 42 Intro. Digital Electronics Fall 2003Latch Operation: PipelinedA2B2C2A2C1B2VDDVOUT-C1CG2Latch 1VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0Latch 0VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0Latch 2A1B1A1VDDVOUT-C2CG1B1Gate 1Gate 1timeClock10timeLowHighLowHighLowHigh5Copyright 2003 , Regents of University of CaliforniaLecture 23: 11/18/03 A.R. NeureutherVersion Date 11/05/03EECS 42 Intro. Digital Electronics Fall 2003Latch Timing DiagramLogic levelTime (inverter delays)0510152025303540ClockL0EXTG1L1INTL1EXTG2L2INTA1 = 0B2 = 1C2 = 0B11 => 0Latency 32 inverter delaysThroughput = 1/(20 x 345ps) = 0.145 GHzP = 20 inverter delaysCopyright 2003 , Regents of University of CaliforniaLecture 23: 11/18/03 A.R. NeureutherVersion Date 11/05/03EECS 42 Intro. Digital Electronics Fall 2003Clock Optimization: PipelinedA2B2C2A2C1B2VDDVOUT-C1CG2Latch 1VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0Latch 0VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0Latch 2A1B1A1VDDVOUT-C2CG1B1Gate 1Gate 1τHIGH= τL_EXT+ max (τGATE1, τGATE2)τLOW= τL_INT6Copyright 2003 , Regents of University of CaliforniaLecture 23: 11/18/03 A.R. NeureutherVersion Date 11/05/03EECS 42 Intro. Digital Electronics Fall 2003Latency and ThroughputLatency L is the delay between the rising edge of the clock on L0 and the data being valid internally in the last latch.LLUMPED= τL_EXT+ τGATE1+ τGATE2+ τL_INT = 2τINV+ 2τINV +2τINV +2τINV = 8τINVLPIPLINED= τL_EXT+ τGATE1+ τL_INT + τL_EXT +τGATE2+ τL_INT = 2τINV+ 2τINV +2τINV +2τINV +2τINV +2τINV = 12τINVThroughput T is the bits per second through the latches and is the maximum clock frequency.PLUMPED= τL_EXT+ τGATE1+ τGATE2+ τL_INT = 2τINV+ 2τINV +2τINV +2τINV = 8τINVPPIPELINED= τL_EXT+ MAX(τGATE1, τGATE2) + τL_INT = 2τINV+ 2τINV +2τINV =6τINVFLUMPED=1/8(345ps) = 0.36 GHzFPIPLINED=1/6(345ps) = 0.48 GHzCopyright 2003 , Regents of University of CaliforniaLecture 23: 11/18/03 A.R. NeureutherVersion Date 11/05/03EECS 42 Intro. Digital Electronics Fall 2003Another ExampleVDDVOUT-LNVDDVMID-LN φφφφCLNCLNVIN-LNA2A2VDDVOUT_2D2B2C2B2C2D2DDSSCL2A1A1C1VDDVOUT_1E1B1D1B1E1D1C1DDSSCL1VDDVOUT-LNVDDVMID-LN φφφφCLNCLNVIN-LNVDDVOUT-LNVDDVMID-LN φφφφCLNCLNVIN-LNL0Gate1
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