Slide 1Clocked LogicDefinition: Combinatorial logicDefinition: Truth tableSequential LogicSlide 6Memory with Cross-coupled GatesTiming BehaviorRace condition on falling edge of S/RDefinition: Race, or Race conditionDefinition: Glitch, HazardDefinition: LatchLevel TriggerGated R-S LatchR-S latch controlled with clockEdge TriggerDefinition: Flip-FlopCascading LatchesMaster-Slave StructureThe 1s Catching ProblemD Flip-FlopEdge triggeringEdge-Triggered Flip-FlopsEdge-Triggered Flip-Flops (cont’d)Slide 25Timing MethodologiesTiming Methodologies (cont’d)Comparison of Latches and Flip-FlopsComparison of Latches and Flip-Flops (cont’d)Typical Timing SpecificationsDefinition: MetastabilityCascading Edge-triggered Flip-FlopsCascading Edge-triggered Flip-Flops (cont’d)Clock SkewSummary of Latches and Flip-Flops11/12/2004 EE 42 fall 2004 lecture 31 1Lecture #31 Flip-Flops, Clocks, Timing•Last lecture: –Finite State Machines•This lecture:–Digital circuits with feedback–Clocks–Flip-Flops11/12/2004 EE 42 fall 2004 lecture 31 2Clocked Logic•In the last few lectures, we have been discussing the implementation of circuits which can break a problem down into a sequence of events, as contrasted with evaluation of a single Boolean expression (Combinatorial Logic)11/12/2004 EE 42 fall 2004 lecture 31 3Definition: Combinatorial logicCombinatorial logic is a set of digital gates which produces an output based solely on its current inputs. A combinatorial logic circuit can be described using a truth table11/12/2004 EE 42 fall 2004 lecture 31 4Definition: Truth table•A Truth table is a description of a digital circuit which is a tabulation of all possible inputs, and the outputs which will result from those inputs.•Two combinatorial logic circuits are considered logically equivalent if they have the same truth table11/12/2004 EE 42 fall 2004 lecture 31 5Sequential Logic•In order to solve more complex problems using a sequence of steps, we looked at the concept of feedback of the output of intermediate results back into the circuit for additional processing. In solving the problems caused by this, we arrived at the finite state machine with latched and clocked feedback.11/12/2004 EE 42 fall 2004 lecture 31 6•In the next two lectures, we will discuss the implementation of sequential logic, latches, clocks, and the various problems which can occur in dynamic digital logic circuits.11/12/2004 EE 42 fall 2004 lecture 31 7RSQQ'RSQR'S'QQQ'S'R'Memory with Cross-coupled Gates•Cross-coupled NOR gates–Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1)•Cross-coupled NAND gates–Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0)11/12/2004 EE 42 fall 2004 lecture 31 8ResetHoldSet SetResetRaceRSQ\Q100Timing BehaviorRSQQ'11/12/2004 EE 42 fall 2004 lecture 31 9Race condition on falling edge of S/R•If both set and reset are high, then the value latched will be whichever falling edge happens last. If this is controlled by delays in the logic, then the outcome of which is first might be random, erratic, or dependent on other parameters.11/12/2004 EE 42 fall 2004 lecture 31 10Definition: Race, or Race condition•A Race condition is when a device's output depends on two [or more] nearly simultaneous events to occur, and where which signal arrives first will change the output of the circuit. If the race condition is so close in time, the output may be unpredictable. When the circuit is manufactured, slight differences can cause a change in the operation of the circuit. A race condition can be a logic hazard, or can result in a random value being held in a latch.11/12/2004 EE 42 fall 2004 lecture 31 11Definition: Glitch, Hazard•A Glitch is a momentary output of a digital circuit of an incorrect value•A Static Hazard is when a single variable change at the input causes a momentary change in the output. •A Dynamic Hazard occurs when a change in the input causes multiple changes in the output.Latches can remove glitches by allowing the output to progress only after the logic has had adequate time to stabilize on the correct output. It is desirable to design out hazard in the logic, because the extra transitions consume power and produce excess noise.If Static Hazards are removed from the design, Dynamic Hazards will not occur. If not removed by latches or Flip-Flops, timing hazards will develop as random or intermittent circuit failures.11/12/2004 EE 42 fall 2004 lecture 31 12Definition: Latch•A latch is a digital circuit which will hold a value when the level of a latching signal is at a certain level. For example, while the reset signal is low, the SR latch will hold the value of Q, (and set it if Set goes high). The alternative is to set the output only at an rising or falling edge, which is referred to as being edge triggered.11/12/2004 EE 42 fall 2004 lecture 31 13Level Trigger•A level trigger refers to the capture of a value while a signal (clock, for example, is high (or low). The data must be held valid and stable during the entire time it is being sampledDataClock11/12/2004 EE 42 fall 2004 lecture 31 14enable'S'Q'QR'RSGated R-S Latch•Control when R and S inputs matter–Otherwise, the slightest glitch on R or S while enable is low could cause change in value storedSetResetS'R'enable'QQ'10011/12/2004 EE 42 fall 2004 lecture 31 15clockR' and S'changing stable changing stablestableR-S latch controlled with clock•Controlling an R-S latch with a clock–Can't let R and S change while clock is active (allowing R and S to pass)–Only have half of clock period for signal changes to propagate–Signals must be stable for the other half of clock periodclock'S'Q'QR'RSactive low11/12/2004 EE 42 fall 2004 lecture 31 16Edge Trigger•Edge Trigger refers to the capture of a value at a rising or falling edge of a signal. For example, the data from a memory might be held valid and sampled at a rising edge of a clockDataClock11/12/2004 EE 42 fall 2004 lecture 31 17Definition: Flip-Flop•A flip flop is a digital circuit which will capture a value at a rising (or falling) edge, and will hold that value. It will only change the value held at an edge, and will not pass on transitions from the inputs while the clock or latch signal is either high or low.11/12/2004 EE 42 fall 2004 lecture 31 18clockRS QQ' RS QQ'RSCascading Latches•Connect output of one latch to input of another•How to stop changes
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