Midterm #2 November 7th, 2001 Closed Book, Closed Notes Write on the Exam paper Print Your Name:____________________ Sign Your Name:____________________ Show your work so that the method as well as the answer can be graded for correctness and completeness. Correct answers alone are only worth 70% of full credit. Problem Possible Score I 30 II 25 III 22 IV 23 Total 100 EECS 42 – Introduction to Electronics for Computer Science Fall 2001, Prof. A. R. Neureuther Dept. EECS, 510 Cory 642-4590 UC Berkeley Tentative OH M, Tu, W, (Th), F 11 Course Web Site http://www-inst.EECS.Berkeley.EDU/~ee42/I (30 Points) Logic and Timing Diagrams Inputs A, B, and C have all been zero (low) for a long time and then at t = 0, A, B and C go to (high) for a long time. a) (5 Points) Find the values of X, Y and Z just before t = 0, and then as t goes to infinity. b) (10 Points) Complete the timing diagram to the right assuming that each gate has a propagation delay of 2 ns before the correct output appears at its output. c) (7 Points) For the CMOS circuit implementation to the right of the NAND gate logic circuit above and the signal changes in part a), find the time at which the change reaches VOUT 1. State the delay in terms of 0.69RC using RU and RD (from the switched resistor device models) and the capacitors shown. d) (8 Points) For the CMOS circuit implementation to the right of the NAND gate logic circuit above and the signal changes in part a), find the time at which the change reaches VOUT 3. State the delay in terms of combinations of 0.69RC using RU and RD (from the switched resistor device models) and the capacitors shown. VDDVOUT 1COUT 1VDDVOUT 2COUT 2VDDVOUT 3COUT 3VDDVOUT 1COUT 1VDDVOUT 1COUT 1VDDVOUT 2COUT 2VDDVOUT 2COUT 2VDDVOUT 3COUT 3VDDVOUT 3COUT 3 Before t =0 As t => infinity X Y Z Time (ns)Logic levelABXYC02468ZTime (ns)Logic levelABXYC02468Z ABCXYZABCXYZ A A A A B B C CII (25 Points) Ideal Op-Amp Analysis Use the ideal op-amp analysis method in this problem. a) (8 Points) Find VOUT1 in terms of the resistances and input voltages. b) (9 Points) Give sufficient additional equations for finding VOUT2 in terms of the resistances and input voltages. Do not solve. c) (8 Points) Assume that VOUT2 = k1V1 + k2V2 + k3V3 + k4V4. For i = 1,4 complete the table below by determining the sign of ki and listing the resistors that will contribute to ki. Hint: Start with what you know from part a) to reach VOUT 1 and then apply this principle again. Term number i Sign of ki Resistors Contributing to ki V1 V2 V3 V4 R3VOUT1R1V1V2R2R4VOUT2R6R5R7R8R9V3V4III (22 Points) Device I vs. V Curves a) (10 Points) For the logic circuit and device characteristics shown find VOUT when VIN = 3V. b) (12 Points) For the logic circuit shown, approximately sketch the voltage transfer function VOUT vs. VIN. Specify values of VOUT for VIN = 0, 3 and 5V. DeviceIOUTOutputVINVDDIS = 40 µARLOAD =100 kΩDeviceIOUTOutputVINVDDIS = 40 µARLOAD =100 kΩ 035IOUT(µA)2060100VIN= 0VVIN= 3VVIN= 1VVIN= 2VVIN= 4 and 5VVOUT(V)035IOUT(µA)2060100IOUT(µA)20601002060100VIN= 0VVIN= 3VVIN= 1VVIN=
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