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Berkeley ELENG 42 - Physical Limitations of Logic Gates

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PowerPoint PresentationSlide 2Slide 3Slide 4EFFECT OF GATE DELAYTIMING DIAGRAMSWHAT IS THE ORIGIN OF GATE DELAY?VOLTAGE WAVEFORMS (TIME FUNCTIONS)GATE DELAY (PROPAGATION DELAY)EFFECT OF PROPAGATION DELAY ON PROCESSOR SPEEDWHAT DETERMINES GATE DELAY?ExampleSimple model for logic delaysSlide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20ENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORS – A REVIEWENERGY AND POWER IN CHARGINGENERGY AND POWER IN CHARGING/DISCHARGING CAPACITORSENERGY IN DISCHARGING CAPACITORSPOWER DISSIPATION in DIGITAL CIRCUITSLOGIC POWER DISSIPATIONLOGIC POWER DISSIPATION with power mitigationW. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaPhysical Limitations of Logic Gates – Week 10aIn a computer we’ll have circuits of logic gates to perform specific functions• Computer Datapath: Boolean algebraic functions using binary variables• Symbolic representation of functions using logic gates• Example:DCAB•Every node has capacitance and interconnects have resistance. It takes time to charge these capacitances.•Thus, output of all circuits, including logic gates is delayed from input.•For example we will define the unit gate delayW. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaUNIT GATE DELAY DTime delay D occurs between input and output: “computation” is not instantaneous Value of input at t = 0+ determines value of output at later time t = DABC0110Logic StatettD00Input (A and B tied together)OutputW. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaUNIT GATE DELAY D in ASYNCHRONOUS LOGICTime delay D is measured from the last input changeABC0110Logic StatettD00Input BOutputInput AW. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaSynchronous and Asynchronous LogicTime delay occurs between input and output in real logic circuits.Therefore the time at which output appears is difficult to predict… it depends for example on how many gates you go through. ABCThus in the modified gate, C will be valid precisely one gate delay (D) after the clock input CK, goes high (A and B are evaluated precisely when CK goes high, what they do before or after this is irrelevant; CK must go low, then high again before the NAND gate again looks at A and B). CKTo make logic operations as fast as possible, we need predictability of signal availability. That is we want to know exactly when “C” is correctly computed from A and B. This requirement argues for synchronous logic, in which a clock signal CK actually initiates the computation of C.We will often not distinguish asynchronous vs synchronous logic.W. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaEFFECT OF GATE DELAYCascade of Logic GatesABCDInputs have different delays, but we ascribe a single worst-case delay D to every gateHow many “gate delays for shortest path? ANSWER : 2How many gate delays for longest path? ANSWER : 3Which path is the important one? ANSWER : LONGESTW. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaC,B,AD)BA( )(__CBBDtttttLogic stateDDD2D2D03DDTIMING DIAGRAMSShow transitions of variables vs timeABCNote that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second.)(__CBNo change at t = 3 DNote becomes valid one gate delay after B switchesBW. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaWHAT IS THE ORIGIN OF GATE DELAY?Logic gates are electronic circuits that process electrical signalsMost common signal for logic variable: voltageNote that the specific voltage range for 0 or 1 depends on “logic family,” and in general decreases with logic generationsSpecific voltage ranges correspond to “0” or “1”Thus delay in voltage rise or fall (because of delay in charging internal capacitances) will translate to a delay in signal timing3210VoltsRange  “0”Range  “1”“Gray area” . . . not allowedW. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaVOLTAGE WAVEFORMS (TIME FUNCTIONS)Inverter input is vIN(t), output is vOUT(t)inside a large system)t(vIN)t(vOUTtVin(t)W. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaApproximationDGATE DELAY (PROPAGATION DELAY)Define  as the delay required for the output voltage to reach 50% of its final value. In this example we will use 3V logic, so halfway point is 1.5V.Inverters are designed so that the gate delay is symmetrical (rise and fall)Vin(t)t1.5Vout(t)t1.5DDW. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaEFFECT OF PROPAGATION DELAY ON PROCESSOR SPEEDComputer architects would like each system clock cycle to have between 20 and 50 gate delays … use 35 for calculationsImplication: if clock frequency = 500 MHz clock period = (5108 s1)1Period = 2  10 9s = 2 ns (nanoseconds)Gate delay must be D = (1/35)  Period = (2 ns)/35 = 57 ps (picoseconds) How fast is this? Speed of light: c = 3  108 m/sDistance traveled in 57 ps is:C X D = (3x108m/s)(57x10-12s) = 17 x 10-4 m = 1.7cmW. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaWHAT DETERMINES GATE DELAY?)t(vIN)t(vOUTThe delay is mostly simply the charging of the capacitors at internal nodes.We already know how to analyze this.W. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaExampleThe gate delay is simply the charging of the capacitors at internal nodes.Oversimplified example using “ideal inverter, II” and 5V logic swing)t(vOUT)t(vIN2.55)t(vIN)t(vOUT RC = 0.1ns so 0.069ns after vIN switches by 5V, Vx moves 2.5VtvIN2.55VxD = 0.069nsvOUT)t(vIN)t(vOUTIIRCVx RC = 0.1ns MODELW. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of University of CaliforniaSimple model for logic delaysModel actual logic gate as an ideal logic gate fed by an RC network which represents the dominant R and C in the gate.)t(vINtvINVXD = 0. 69 RCvOUT)t(vIN)t(vOUTRCIdeal Logic gateActual Logic GateIdeal Logic gatetVX)t(vOUTetc.W. G. OldhamEECS 42 Spring 2001 Lecture 19 Copyright Regents of


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Berkeley ELENG 42 - Physical Limitations of Logic Gates

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