PowerPoint PresentationMemory typesRAMTypes of memoryOther types of memoryRAM logical organizationSRAMStatic RAM (SRAM)SRAM cellDRAMDynamic RAMBasic DRAM CellDRAM OperationsAdvanced DRAM CellsSlide 15DRAM logical organization (4 Mbit)DRAM sense ampDRAM sense amplifierDRAM/SRAM tradeoffsFLASH MemoryMore esoteric Storage Technologies?Tunneling Magnetic Junction11/29/2004 EE 42 fall 2004 lecture 37 1Lecture #37: Memory•Last lecture:–Transmission line equations–Reflections and termination–High frequency measurements•This lecture:–Static Ram–Dynamic Ram11/29/2004 EE 42 fall 2004 lecture 37 2Memory types•In addition to registers, there is usually a need in digital logic devices for a denser (and therefore cheaper) means of storing information in larger amounts.•The main memory types are known as RAM (Random Access Memory) as contrasted with long shift registers from which information can only be extracted or added in sequence.11/29/2004 EE 42 fall 2004 lecture 37 3RAM•In a RAM, an address is provided to a block of logic, along with an address strobe and a write signal line.•The memory block then either reads a block of bits and puts it onto a bus, or writes the data from the bus into the indicated area of memory.11/29/2004 EE 42 fall 2004 lecture 37 4Types of memory•SRAM (Static RAM) is a memory which is essentially an array of flip flops. It can be very fast, and is integrated with logic.•DRAM (Dynamic RAM) is a dense memory which uses a single capacitor controlled by a switch to store a bit. Dram must be rewritten after a write, and must be refreshed periodically.11/29/2004 EE 42 fall 2004 lecture 37 5Other types of memory•Read only memory (ROM) is a memory whose content is fixed at manufacture, and thus can only be read.•Content addressable memory (CRAM) is memory which can be addressed, at least in part by its contents, rather than an address.•E2 memory (electrically erasable) is memory which can be read and written, but whose content is nonvolatile. Writing is often much slower than reading11/29/2004 EE 42 fall 2004 lecture 37 6RAM logical organization Note that the number row decoder lines and column lines goes like the square root of the memory sizeColumn DecoderMemory array …DQRow Decoder…Address linesAddress strobeRead/Write11/29/2004 EE 42 fall 2004 lecture 37 7SRAM•Cache uses SRAM: Static Random Access Memory–No refresh –Size 6 transistors/bit –Fast, can be optimized for speed or area reduction–Compatible with dense logic, so can be integrated with microprocessors with no extra masks11/29/2004 EE 42 fall 2004 lecture 37 8Static RAM (SRAM)•Six transistors in cross connected fashion–Provides regular AND inverted outputs–Implemented in CMOS processSingle Port 6-T SRAM Cell11/29/2004 EE 42 fall 2004 lecture 37 9SRAM cell•Each cell of an SRAM is a pair of cross connected small inverters•As long as power is supplied, the latch will hold the value.•When the row line is held high, the outputs are driven with the contents of the memory. •The latch is written by using a more powerful driver on the column lines to overcome the smaller transistors in the latch which forces the desired state.11/29/2004 EE 42 fall 2004 lecture 37 10DRAM•Main Memory is DRAM: Dynamic Random Access Memory–1 transistor–Dynamic since needs to be refreshed periodically (8 ms, 1% time)–Addresses divided into 2 halves (Memory as a 2D matrix):•RAS or Row Access Strobe•CAS or Column Access Strobe11/29/2004 EE 42 fall 2004 lecture 37 11•SRAM cells exhibit high speed/poor density•DRAM: simple transistor/capacitor pairs in high density formDynamic RAMWord LineBit LineCSense Amp...11/29/2004 EE 42 fall 2004 lecture 37 12Basic DRAM Cell•Planar Cell–Polysilicon-Diffusion Capacitance, Diffused Bitlines•Problem: Uses a lot of area (< 1Mb)•You can’t just ride the process curve to shrink C (discussed later)(a) Cross-section(b) LayoutDiffusedbit linePolysiliconplateM1 wordlineCapacitorPolysilicongateMetal word lineSiO2n+Field OxideInversion layerinduced by plate biasn+polypolyUsed Polysilicon-Diffusion CapacitanceExpensive in Area11/29/2004 EE 42 fall 2004 lecture 37 13DRAM Operations•Write–Charge bitline HIGH or LOW and set wordline HIGH•Read–Bit line is precharged to a voltage halfway between HIGH and LOW, and then the word line is set HIGH. –Depending on the charge in the cap, the precharged bitline is pulled slightly higheror lower.–Sense Amp Detects change•The signal is decreased by the ratio of the storage capacitance to the bitline capacitance–Increase density => increase parasiticcapacitance–As geometries shrink, still need large bit capacitanceWord LineBit LineCSense Amp...11/29/2004 EE 42 fall 2004 lecture 37 14Advanced DRAM Cells•Stacked cell (Expand UP)11/29/2004 EE 42 fall 2004 lecture 37 15Advanced DRAM Cells•Trench Cell (Expand DOWN)Cell Plate SiCapacitor InsulatorStorage Node Poly2nd Field OxideRefilling PolySi Substrate11/29/2004 EE 42 fall 2004 lecture 37 16DRAM logical organization (4 Mbit)•Square root of bits per RAS/CASColumn DecoderSense Amps & I/OMemory Array(2,048 x 2,048)A0…A10…11DQWord LineStorage CellRow Decoder…11/29/2004 EE 42 fall 2004 lecture 37 17DRAM sense ampenableenableenableenableBit lineBoth precharged to ½ V Data out+V11/29/2004 EE 42 fall 2004 lecture 37 18DRAM sense amplifier•The reason that DRAM is slow, is that a very small charge is captured on the capacitor, and the small voltage change on the line must be sensed. timeVPrecharge→Charge dumped to bit lineSense amp decides 0 or 111/29/2004 EE 42 fall 2004 lecture 37 19DRAM/SRAM tradeoffs•By it’s nature, DRAM isn’t built for speed–Response time dependent on capacitive circuit properties which get worse as density increases•DRAM process isn’t easy to integrate into CMOS process–DRAM is off chip –Connectors, wires, etc introduce slowness–IRAM efforts looking to integrating the two•Memory Architectures are designed to minimize impact of DRAM latency–Use dram for high density, store data which is used often in smaller, higher speed SRAM cache.11/29/2004 EE 42 fall 2004 lecture 37 20FLASH Memory•Floating gate transistor–Presence of charge => “0”–Erase Electrically or UV (EPROM)•Performance–Reads like DRAM (~ns)–Writes like DISK (~ms). Write is a complex operation11/29/2004 EE 42 fall 2004 lecture 37 21•Tunneling Magnetic Junction RAM (TMJ-RAM):–Speed of SRAM, density of
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