Week 12a, Slide 1EECS42, Spring 2005 Prof. WhiteWeek 12aOUTLINE– Sequential logic circuits–Fan-out– Propagation delay– CMOS power consumptionReading: Hambley Ch. 7; Rabaey et al. Sec. 5.2Week 12a, Slide 2EECS42, Spring 2005 Prof. WhiteFlip-Flops• One of the basic building blocks for sequential circuits is the flip-flop:– 2 stable operating states Æ stores 1 bit of info.– A simple flip-flop can be constructed using two inverters:QQWeek 12a, Slide 3EECS42, Spring 2005 Prof. White• Rule 1:–If S = 0 and R = 0, Q does not change.• Rule 2: –If S = 0 and R = 1, then Q = 0• Rule 3:–If S = 1 and R = 0, then Q = 1• Rule 4:– S = 1 and R = 1 should never occur.The S-R (“Set”-“Reset”) Flip-FlopSRQS-R Flip-Flop Symbol:QWeek 12a, Slide 4EECS42, Spring 2005 Prof. WhiteRealization of the S-R Flip-FlopSRQQ(not allowed)11001110Qn-100QnSRWeek 12a, Slide 5EECS42, Spring 2005 Prof. WhiteClock Signals• Often, the operation of a sequential circuit is synchronized by a clock signal :• The clock signal regulates when the circuits respond to new inputs, so that operations occur in proper sequence.• Sequential circuits that are regulated by a clock signal are said to be synchronous.timevC(t)VOH0TC2TCpositive-going edge(leading edge)negative-going edge(trailing edge)Week 12a, Slide 6EECS42, Spring 2005 Prof. WhiteClocked S-R Flip-Flop• When CK = 0, the value of Q does not change• When CK = 1, the circuit acts like an ordinary S-R flip-flopSRQQCKWeek 12a, Slide 7EECS42, Spring 2005 Prof. White• The output terminals Q and Q behave just as in the S-R flip-flop.• Q changes only when the clock signal CKmakes a positive transition.The D (“Delay”) Flip-FlopDCKQD Flip-Flop Symbol:Q11↑00↑Qn-1×1Qn-1×0QnDCKWeek 12a, Slide 8EECS42, Spring 2005 Prof. WhiteD Flip-Flop Example (Timing Diagram)tCKtDtQWeek 12a, Slide 9EECS42, Spring 2005 Prof. WhiteRegisters•A register is an array of flip-flops that is used to store or manipulate the bits of a digital word.Example: Serial-In, Parallel-Out Shift RegisterD0CKQ0Data inputClock inputD1CKQ1D2CKQ2Q0Q1Q2Parallel outputsWeek 12a, Slide 10EECS42, Spring 2005 Prof. WhiteConclusion (Logic Circuits)• Complex combinational logic functions can be achieved simply by interconnecting NAND gates (or NOR gates).• Logic gates can be interconnected to form flip-flops.• Interconnections of flip-flops form registers.• A complex digital system such as a computer consists of many gates, flip-flops, and registers. Thus, logic gates are the basic building blocks for complex digital systems.Week 12a, Slide 11EECS42, Spring 2005 Prof. WhiteFan-Out• Typically, the output of a logic gate is connected to the input(s) of one or more logic gates• The fan-out is the number of gates that are connected to the output of the driving gate:•••fan-out =Ndriving gate12N• Fanout leads to increased capacitive load on the driving gate, and therefore longer propagation delay– The input capacitances of the driven gates sum, and must be charged through the equivalent resistance of the driverWeek 12a, Slide 12EECS42, Spring 2005 Prof. WhiteEffect of Capacitive Loading• When an input signal of a logic gate is changed, there is a propagation delay before the output of the logic gate changes. This is due to capacitive loading at the output.CL+vOUT−+vIN−vINvOUTThe propagation delay ismeasured between the50% transition points ofthe input and output signals.Week 12a, Slide 13EECS42, Spring 2005 Prof. WhiteModel the MOSFET in the ON state as a resistive switch:Case 1: Voutchanging from High to Low(input signal changed from Low to High) NMOSFET(s) connect Voutto GNDtpHL= 0.69×RnCLCalculating the Propagation DelayVDDPull-down network is modeled as a resistorPull-up network is modeled as an open switchCL+vOUT−vIN= VDDRnWeek 12a, Slide 14EECS42, Spring 2005 Prof. WhiteCalculating the Propagation Delay (cont’d)Case 2: Voutchanging from Low to High(input signal changed from High to Low) PMOSFET(s) connect Voutto VDDtpLH= 0.69×RpCLVDDRpPull-down network is modeled as an open switchPull-up network is modeled as a resistorCL+vOUT−vIN= 0 VWeek 12a, Slide 15EECS42, Spring 2005 Prof. WhiteOutput Capacitance of a Logic Gate• The output capacitance of a logic gate is comprised of several components:• pn-junction and gate-drain capacitance– both NMOS and PMOS transistors• capacitance of connecting wires• input capacitances of the fan-out gates“extrinsiccapacitance”“intrinsiccapacitance”Impact of gate-drain capacitanceWeek 12a, Slide 16EECS42, Spring 2005 Prof. WhiteMinimizing Propagation Delay• A fast gate is built by 1. Keeping the output capacitance CLsmall– Minimize the area of drain pn junctions.– Lay out devices to minimize interconnect capacitance.– Avoid large fan-out.2. Decreasing the equivalent resistance of the transistors– Decrease L– Increase W… but this increases pn junction area and hence CL3. Increasing VDD→ trade-off with power consumption & reliabilityWeek 12a, Slide 17EECS42, Spring 2005 Prof. WhiteTransistor Sizing for Performance• Widening the transistors reduces resistance, but increases capacitance• In order to have the on-state resistance of the PMOS transistor match that of the NMOS transistor (e.g. to achieve a symmetric voltage transfer curve), its W/L ratio must be larger by a factor of ~3. To achieve minimum propagation delay, however, the optimum factor is ~2.VDDVINVOUTSDGGSDWeek 12a, Slide 18EECS42, Spring 2005 Prof. WhiteCMOS Energy Consumption (Review)• The energy delivered by the voltage source in charging the load capacitance is– Half of this is stored in CL; the other half is absorbed by the resistance through which CLis charged.→ In one complete cycle (charging and discharging), the total energy delivered by the voltage source isRnVDD+−CLRp2DDLVC2DDLVCvIN= 0 VvIN= VDDWeek 12a, Slide 19EECS42, Spring 2005 Prof. WhiteCMOS Power Consumption• The total power consumed by a CMOS circuit is comprised of several components:1. Dynamic power consumption due to charging and discharging capacitances*:f0Æ1= frequency of 0Æ1 transitions (“switching activity”)f = clock rate (maximum possible event rate)Effective capacitance CEFF= average capacitance charged every clock cycle* This is typically by far the dominant component!fVCfVCPDDEFFDDLdyn2102==→Week 12a, Slide 20EECS42, Spring 2005 Prof. WhiteCMOS Power Consumption (cont’d)2. Dynamic power consumption due
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