Tutorial on FPGA Design Flow based on Aldec Active HDL Ver 1 6 1 Prepared by Ekawat Ice Homsirikamol Marcin Rogawski Jeremy Kelly Kishore Kumar Surapathi Ambarish Vyas and Dr Kris Gaj This tutorial assumes that you have basic knowledge on how to use ActiveHDL and its functional simulation The example codes used in this tutorial can be obtained from http ece gmu edu coursewebpages ECE ECE448 S11 tutorials Aldec Active HDL Simulation pdf The current version of the tutorial was tested using the following tools CAD Tool ActiveHDL Synthesis Tool o ISE Webpack Synthesis Implementation Implementation Tool o Xilinx ISE WebPack Versions 7 2 8 2 8 3 Version 9 1 10 1 12 2 12 4 Version 9 1 10 1 12 2 12 4 FPGA Board Digilent Basys2 Combinations of tools supported as of Fall 2010 are as follows At home Aldec Active HDL Student Edition ver 7 2 Xilinx ISE Webpack 9 1 SP3 At GMU Aldec Active HDL ver 8 3 Xilinx ISE Webpack 9 1 10 1 11 4 12 2 or 12 4 2 Table of Contents 1 2 3 4 Project Settings 4 Synthesis 2 1 Synthesis using Xilinx XST 2 1 1 Synthesis Options 2 1 2 Synthesis Reports Analysis 2 2 Post Synthesis Simulation 13 15 17 Implementation 3 1 Implementation Options 3 2 Implementation Reports Analysis 3 3 Post Implementation Simulation 18 21 28 Uploading Bitstream to FPGA Board 29 3 1 Project Settings 4 5 Create new workspace and choose Create an Empty Design with Design Flow Then press Next You will see a picture similar to the one shown below Verify that Flow Configuration Settings are defined as followed Synthesis Tool Xilinx ISE WebPack version number XST Implementation Tool Xilinx ISE WebPack version number Default Family Xilinx version number x SPARTAN3 If not click at the Flow Configuration Settings button and adjust appropriately 6 Also choose Block Diagram Configuration Default HDL Language Default HDL Language VHDL Once done select Next Finish 7 8 Specify the new design name Download to your hard drive all VHDL files provided to you at the website for lab3 demo Add and compile all files from lab3 demo Then test your design if it works correctly in the functional simulation as you would normally do If you are following the tutorial by using lab3demo make sure you change the slow clock period located inside Lab3Demo package vhd to a number suitable for simulation 5 It will take a long time to simulate otherwise 9 10 Now you should see a screen divided into several parts with a Flow panel on the right side If you do not see the Flow panel on the right side as shown in the picture you can press Alt 3 or View Flow from the top menu bar to open the panel Go to Tools Preferences In category expand Flows Integrated tools If the tool for HDL synthesis and Implementation are already selected then click on OK If not choose the tools as shown below and the path accordingly 11 12 2 Synthesis Synthesis can be done using Xilinx XST 2 1 Synthesis using Xilinx XST 2 1 1 Synthesis Options 13 Click at the options button next to the synthesis icon Under Synthesis Options select Update synthesis order Arrange your files in the order from the bottom to the top of the design hierarchy Exclude your non synthesizable files such as testbench Also select a correct Top level Unit which is Lab3 demo in the example you follow Make sure that your settings under General tab are as follows Family Xilinx12x Spartan3 Device 3s50pq208 Speed Grade 4 Under Std Synthesis and Adv Synthesis tabs you can adjust optimization goal of the synthesis tool for various results Most notably you can tell the synthesis tool to optimize for either area or speed To select either one of them choose Std Synthesis Optimization Goal select Speed or Area 14 2 1 2 Synthesis Report Analysis Minimum clock period critical path and resource utilization can be found from the log file generated after synthesis To view the log file click at the reports button next to the Synthesis icon Minimum clock period maximum frequency and critical path can be found under Timing Summary section Looking at the critical paths can give you an idea of which portions of your code to change in order to improve the circuit performance Resource utilization is located in the Final Report section Example Report Resource Utilization 15 Example Report Minimum Clock Period and Critical Path 16 2 2 Post Synthesis Simulation Click at the options button next to the post synthesis simulation icon Remove the default input file and select your testbench as an input file by clicking at the button close to the cross sign marked by a dot Then select Recompile Files Once done choose the appropriate top level unit which is lab3demo tb vhd in this example Press OK and then select post synthesis simulation Now you should see timing waveforms similar to the ones obtained during functional simulation The difference is that the components and signals are now mapped into appropriate FPGA hardware 17 3 Implementation 3 1 Implementation Options Click at the options button next to the implementation icon Select the correct Netlist File which is a file with the same name as your top level VHDL file and the extension edf It is normally located in the synthesis folder of your workspace Use this file to implement your design Choose the correct FPGA Family Device and Speed Grade the same as used during the Synthesis phase In our example these are Family Xilinx11x Spartan3 Device 3s50pq208 Speed Grade 4 Under Constraint File select Custom constraint file Browse to your ucf for the lab lab3 demo ucf in our example Then navigate to the BitStream tab by clicking at the right arrow at the top right hand 18 corner Under General tab of BitStream deselect Do Not Run Bitgen This will create bitstream bit which you can upload to FPGA Also under Post Map STR Post PAR STR and Simulation tabs make sure that your device speed grade is set to 4 You can also specify the implementation tool to use a certain optimization goal To do this go to Advanced Map Optimization Goal select either Area or Speed 19 Press OK and then select implementation 20 3 2 Implementation Reports Analysis Similarly to synthesis you can access the generated reports by clicking the reports button near the implementation icon Unlike synthesis log implementation log is divided into several smaller reports which are named differently Below is a list of reports in which you can find the most useful information about your design after implementation such as resource utilization maximum clock frequency and critical path 21 Resource Utilization
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