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MASON ECE 448 - Lecture 16 ASIC Front-End Design

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ASIC Front-End DesignSlide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Simplified ASIC Design FlowMajor ASIC ToolsetsSlide 13A Complete Placed and Routed ChipWhat is “Physical Layout”?Process of Device FabricationWafer Representation of Layout PolygonsSlide 18Simplified RTL SynthesisVHDL vs. VerilogSlide 21Logic SynthesisTCL – Tool Command LanguageTCL ExampleTCL ReferencesSlide 26Slide 27Slide 28Slide 29Synthesis script (1)Synthesis script (2)Synthesis script (3)Synthesis script (4)Slide 34Slide 35Synthesis script (5)Slide 37Area report after synthesis (1)Area report after synthesis (2)Critical Path (1)Critical Path (2)Slide 42Clock JitterClock SkewTiming report after synthesis (1)Timing report after synthesis (2)Timing report after synthesis (3)Timing report after synthesis (4)Timing report after synthesis (5)Timing report after synthesis (6)Timing report after synthesis (7)Slide 52Static Timing Analysis ReviewReview of Setup and Hold ChecksFalse and Multicycle pathsMulticycle path - ExampleSlide 57Slide 58Slide 59Slide 60Recommended rules for SynthesisAvoid hierarchical combinational blocksRecommend way to handle Combinational PathsRegister all outputsNO GLUE LOGIC between blocksSeparate design with different goalsOptimization based on design requirementsSeparate FSM with random logicMaintain a reasonable block sizeECE 448 – FPGA and ASIC Design with VHDL George Mason UniversityASIC Front-End DesignECE 448Lecture 16ECE 448 – FPGA and ASIC Design with VHDL 2• designs must be sent for expensive and time consuming fabrication in semiconductor foundry• bought off the shelf and reconfigured by designers themselvesTwo competing implementation approachesASICApplication SpecificIntegrated CircuitFPGAField ProgrammableGate Array• designed all the way from behavioral description to physical layout• no physical layout design; design ends with a bitstream used to configure a deviceECE 448 – FPGA and ASIC Design with VHDL 3FPGAs vs. ASICsASICsFPGAsHigh performanceOff-the-shelfShort time to the marketLow development costsReconfigurabilityLow powerLow cost (but only in high volumes)ECE 448 – FPGA and ASIC Design with VHDL 4Local MemoryGlobal MemoryASIC Design Example – Factoring circuit/GMUECE 448 – FPGA and ASIC Design with VHDL 551xASIC 130 nm vs. Virtex II 6000Factoring/GMU19.80 mm19.68 mm2.7 mm2.82 mmArea of Xilinx Virtex II 6000FPGA (estimation by R.J. Lim Fong, MS Thesis, VPI, 2004) Area of an ASIC with equivalent functionalityECE 448 – FPGA and ASIC Design with VHDL 6Source:I. Kuon, J. Rose,University of Toronto“Measuring the Gap Between FPGAs and ASICs”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,vol. 62, no. 2, Feb 2007.ASICs vs. FPGAsECE 448 – FPGA and ASIC Design with VHDL 7ECE 448 – FPGA and ASIC Design with VHDL 8ECE 448 – FPGA and ASIC Design with VHDL 9ECE 448 – FPGA and ASIC Design with VHDL 10ECE 448 – FPGA and ASIC Design with VHDL 11Simplified ASIC Design FlowSynthesisSynthesisPlacementPlacementClock Tree SynthesisClock Tree SynthesisRoutingRoutingFloorplanningFloorplanningTiming AnalysisTiming AnalysisDesign for ManufacturingDesign for Manufacturing31Front-EndDesignBack-EndDesignECE 448 – FPGA and ASIC Design with VHDL 12Major ASIC ToolsetsCadenceMagmaECE 448 – FPGA and ASIC Design with VHDL 13Simplified ASIC Design FlowSynthesisSynthesisPlacementPlacementClock Tree SynthesisClock Tree SynthesisRoutingRoutingFloorplanningFloorplanningTiming AnalysisTiming AnalysisDesign for ManufacturingDesign for Manufacturing31Front-EndDesignBack-EndDesignSynopsys ToolsDesign AnalyzerPrimetimeAstroECE 448 – FPGA and ASIC Design with VHDL 14A Complete Placed and Routed ChipIP28ECE 448 – FPGA and ASIC Design with VHDL 15What is “Physical Layout”?Physical Layout – Topography of devices and interconnects, made up of polygons that represent different layers of material (diffusion, polysilicon, metal, contact, etc) NMOSPMOSOUTVDDGNDPhysical or Layout ViewININOUTPMOSNMOSTransistor or Device ViewVDDGNDECE 448 – FPGA and ASIC Design with VHDL 16Layout or Mask (aerial) viewSilicon SubstrateProcess of Device Fabrication•Devices are fabricated vertically on a silicon substrate wafer by layering different materials in specific locations and shapes on top of each other•Each of many process masks defines the shapes and locations of a specific layer of material (diffusion, polysilicon, metal, contact, etc)•Mask shapes, derived from the layout view, are transformed to silicon via photolithographic and chemical processesWafer (cross-sectional) view40ECE 448 – FPGA and ASIC Design with VHDL 17Wafer Representation of Layout PolygonsInputVDDGNDOutputPMOSNMOS0.25 umAerial or Layout ViewWafer Cross-sectional View41ECE 448 – FPGA and ASIC Design with VHDL 18Front-End Design FlowECE 448 – FPGA and ASIC Design with VHDL 19Simplified RTL SynthesisWrite RTL HDLCodeSimulateOKSynthesize RTLCode to GatesConstraintsMet?Gate LevelTestingOK?HDLNoYesGate LevelNetlistNoYesNoYesProceed withBackendProcessingECE 448 – FPGA and ASIC Design with VHDL 20 VHDL vs. VerilogGovernment DevelopedCommercially DevelopedAda based C basedStrongly Type Cast Mildly Type CastDifficult to learn Easy to LearnMore Powerful Less PowerfulECE 448 – FPGA and ASIC Design with VHDL 21architecture MLU_DATAFLOW of MLU issignal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;beginA1<=A when (NEG_A='0') elsenot A;B1<=B when (NEG_B='0') elsenot B;Y<=Y1 when (NEG_Y='0') elsenot Y1;MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;with (L1 & L0) selectY1<=MUX_0 when "00",MUX_1 when "01",MUX_2 when "10",MUX_3 when others;end MLU_DATAFLOW;VHDL descriptionCircuit netlistLogic SynthesisECE 448 – FPGA and ASIC Design with VHDL 22Logic SynthesisECE 448 – FPGA and ASIC Design with VHDL 23TCL – Tool Command Language•Created by John Ousterhout of UC Berkeley•Scripting Language•Very simple to automate routine tasks.•Extension Language•Used to customize tools with user/company specific aplications.•Nearly all of modern EDA tools have a TCL interface.•Very simple to learn and use.ECE 448 – FPGA and ASIC Design with VHDL 24TCL Exampleproc rfmdIfNotDirMkdir { directory } { if {! [file exists $directory]} { file mkdir $directory; } if {! [file isdirectory $directory]} { echo "Could not make \"$directory\""; exit 1;


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MASON ECE 448 - Lecture 16 ASIC Front-End Design

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