VHDL RefresherRequired readingRecommended readingSlide 4Slide 5VHDLGenesis of VHDLA Brief History of VHDLFour versions of VHDLSlide 10VerilogVHDL vs. VerilogSlide 13Features of VHDL and VerilogSlide 15Naming and Labeling (1)Naming and Labeling (2)Valid or invalid?Free FormatReadability standards & coding styleCommentsSlide 22Slide 23Example: NAND GateExample VHDL CodeDesign EntityEntity DeclarationEntity declaration – simplified syntaxPort Mode INPort Mode OUTPort Mode OUT (with extra signal)Port Mode BUFFERPort Mode INOUTPort Modes - SummaryArchitecture (Architecture body)Architecture – simplified syntaxEntity Declaration & ArchitectureSlide 38Slide 39Slide 40Library DeclarationsLibrary declarations - syntaxFundamental parts of a libraryLibrariesSlide 45STD_LOGICBIT versus STD_LOGICSTD_LOGIC type demystifiedMore on STD_LOGIC Meanings (1)More on STD_LOGIC Meanings (2)Slide 51More on STD_LOGIC Meanings (4)Resolving logic levelsSTD_LOGIC RulesSlide 55SignalsStandard Logic VectorsVectors and ConcatenationFixed Rotation in VHDLFixed Shift in VHDLSlide 61VHDL Design StylesSlide 63Entity xor3_gateDataflow Architecture (xor3_gate)Dataflow DescriptionStructural Architecture in VHDL 87xor2Structural Architecture in VHDL 93Structural DescriptionBehavioral Architecture (xor3 gate)Behavioral Description?George Mason UniversityECE 448 – FPGA and ASIC Design with VHDLVHDL RefresherLecture 22ECE 448 – FPGA and ASIC Design with VHDLRequired reading• P. Chu, FPGA Prototyping by VHDL ExamplesChapter 1, Gate-level combinational circuit• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 2.10, Introduction to VHDL3ECE 448 – FPGA and ASIC Design with VHDLRecommended reading• Wikipedia – The Free On-line Encyclopedia VHDL - http://en.wikipedia.org/wiki/VHDL Verilog - http://en.wikipedia.org/wiki/Verilog4ECE 448 – FPGA and ASIC Design with VHDLRecommended reading• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 6, Combinational-circuit building blocksRequired for Lab 1!Opportunity for bonus points during the next two lectures!• P. Chu, FPGA Prototyping by VHDL ExamplesChapter 3, RT-level combinational circuit5ECE 448 – FPGA and ASIC Design with VHDLBrief History of VHDL6ECE 448 – FPGA and ASIC Design with VHDLVHDL•VHDL is a language for describing digital hardware used by industry worldwide•VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language7ECE 448 – FPGA and ASIC Design with VHDLGenesis of VHDL•Multiple design entry methods and hardware description languages in use•No or limited portability of designs between CAD tools from different vendors•Objective: shortening the time from a design concept to implementation from 18 months to 6 monthsState of art circa 19808ECE 448 – FPGA and ASIC Design with VHDLA Brief History of VHDL•June 1981: Woods Hole Workshop•July 1983: contract awarded to develop VHDL•Intermetrics•IBM•Texas Instruments•August 1985: VHDL Version 7.2 released•December 1987: VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standard9ECE 448 – FPGA and ASIC Design with VHDLFour versions of VHDL•Four versions of VHDL:•IEEE-1076 1987•IEEE-1076 1993 most commonly supported by CAD tools•IEEE-1076 2000 (minor changes)•IEEE-1076 2002 (minor changes)10ECE 448 – FPGA and ASIC Design with VHDLVerilog11ECE 448 – FPGA and ASIC Design with VHDLVerilog•Essentially identical in function to VHDL•No generate statement•Simpler and syntactically different•C-like•Gateway Design Automation Co., 1985•Gateway acquired by Cadence in 1990•IEEE Standard 1364-1995•Early de facto standard for ASIC programming•Programming language interface to allow connection to non-Verilog code12ECE 448 – FPGA and ASIC Design with VHDL VHDL vs. VerilogGovernment DevelopedCommercially DevelopedAda based C basedStrongly Type Cast Mildly Type CastCase-insensitive Case-sensitiveDifficult to learn Easier to LearnMore Powerful Less Powerful13ECE 448 – FPGA and ASIC Design with VHDLHow to learn Verilog by yourself ?14ECE 448 – FPGA and ASIC Design with VHDLFeatures of VHDL and Verilog•Technology/vendor independent•Portable•Reusable15ECE 448 – FPGA and ASIC Design with VHDLVHDL Fundamentals16ECE 448 – FPGA and ASIC Design with VHDLNaming and Labeling (1)•VHDL is case insensitiveExample:Names or labelsdatabusDatabusDataBusDATABUSare all equivalent17ECE 448 – FPGA and ASIC Design with VHDLNaming and Labeling (2)General rules of thumb (according to VHDL-87)1. All names should start with an alphabet character (a-z or A-Z)2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)3. Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)4. Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid)5. All names and labels in a given entity and architecture must be unique18ECE 448 – FPGA and ASIC Design with VHDLValid or invalid?7segment_displayA87372477424Adder/Subtractor/resetAnd_or_gateAND__OR__NOTKogge-Stone-AdderRipple&Carry_AdderMy adder19ECE 448 – FPGA and ASIC Design with VHDLFree Format•VHDL is a “free format” language No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way.Example:if (a=b) thenorif (a=b) then orif (a =b) thenare all equivalent20ECE 448 – FPGA and ASIC Design with VHDLReadability standards & coding styleAdopt readability standards based on one of the the two main textbooks:Chu or Brown/VranesicUse coding style recommended in OpenCores Coding Guidelineslinked from the course web pageStrictly enforced by the lab instructors and myself.Penalty points may be enforced for not followingthese recommendations!!!21ECE 448 – FPGA and ASIC Design with VHDLComments•Comments in VHDL are indicated with a “double dash”, i.e., “--”Comment indicator can be placed anywhere in the lineAny text that follows in the same line is treated as a commentCarriage return terminates a commentNo method for commenting a block extending over a couple of linesExamples:-- main subcircuitData_in <= Data_bus; -- reading data from the input FIFO22ECE 448 – FPGA and ASIC Design with VHDLComments•Explain Function of Module to Other Designers•Explanatory, Not Just Restatement of Code•Locate
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