1Tutorial onFPGA Design Flowbased onXilinx ISE Webpackand ModelSimver. 2.02Prepared by Marcin Rogawski, Ekawat (Ice) Homsirikamol, and Dr. Kris GajThe example codes used in this tutorial can be obtained fromhttp://ece.gmu.edu/coursewebpages/ECE/ECE448/S09/experiments/448_lab3.htm.The current version of the tutorial was tested using the following tools:CAD Tool Xilinx ISE Webpack Version : 9.1Synthesis Tool ISE&Webpack Synthesis&Implementation Version : 9.1 Synplicity Synplify Pro Version : 8.6Implementation Tool Xilinx ISE/WebPack Version : 9.1FPGA Board Celoxica RC103Table of Contents1. Project Settings 42. Behavioral Simulation 73. Pin Assignment 94 Synthesis and Implementation 114.1 Synthesis 114.1.1 Synthesis with Xilinx XST 114.1.2 Synthesis with Synplify Pro 134.2 Translate 154.3 Post-Translate Simulation 164.4 Map 184.5 Place and Route 194.6 Post Place and Route Simulation 204.7 Implementation Reports 214.6 Bit Stream Generation 225. Uploading Bitstream to FPGA Board 2341. Project SettingsTo Start Xilinx ISE go to:Start->All Programs-> VLSI Tools->Xilinx ISE 9.1i->Project NavigatorTo start new Project go to: menu File->New Project5Specify Project Name and location for project filesClick Next and specifyFamily : Xilinx9x Spartan3Device : 3s1500Package : fg320Speed Grade : -4Simulator : ModelSim SE VHDL6Click Next and then Add Source. Choose files for the project.Then click Open and Finish. Your project has been defined.72. Behavioral simulationIn the menu Sources for we choose Behavioral Simulation. The testbench for this design was set as atop level. In the menu Processes for choose ModelSim Simulator, right-click and choose Run.You will see a picture similar to the one above.8Finally you should be able to observe waveforms for your design.93. Pin AssignmentGo to menu Sources for and change this option to Synthesis/Implementation. Click on AssignPackage Pins. The User Constraint File (UCF) will be created if you decide to assign design port names to thephysical pins. Columns I/O Names and I/O Descriptions represent ports from your design. The Loc columnshould be used to input the location of the corresponding pin in the FPGA device.10We can specify Pin Assignments by going to User Constraint menu. We can assign design port namesto the physical pins of a chosen device by option Edit Constraints (Text). Keyword NET is for a port nameassignment and keyword LOC is for a physical pin assignment.114. Synthesis and Implementation4.1 Synthesis4.1.1 Synthesis with Xilinx XSTGo to the menu Sources for and change this option to Synthesis/Implementation. Click Check Syntax tocheck if vhdl sources are properly coded.When you right-click on Generate Post-Synthesis Simulation Model then pop-up menu appears. ChooseRunto start synthesis (There is no option to simulate post-synthesis netlist for Xilinx ISE WebPack).12Synthesis and generation of Post-Synthesis Simulation Model were completed successfully and we canstart Implementation part.134.1.2 Synthesis with Simplify ProThere is a possibility in Xilinx ISE to specify other vendors of synthesis software. Go to Sources formenu, right-click on the name of the chosen design. Pop-up menu should appear. Choose Properties.The Project Properties menu should be available now. Change Synthesis Tool to Synplify Pro(VHDL/Verilog). Click OK – your design will use Synplify Pro for synthesis.14When Synthesis process is completed, the report from synthesis becomes available. Some of the mostimportant features of the design are the minimum clock period and the maximum clock frequency. We can findthese two parameters in the report file from Synthesis. Please remember that the values of these parameters aftersynthesis are different than the values of the same parameters after implementation.The other important information we can find in this report is the amount of FPGA resources your designrequires.154.2 TranslateThe first step in the Xilinx Design Flow for implementation is Translate. Under Implement Designoption, choose Translate, and then Run.If you are successful with this part you should generate Post Translate Simulation Model.164.3 Post-Translate SimulationWhen you right-click on Generate Post-Translate Simulation Model then pop-up menu appears.Choose Run to start.In the menu Sources for we choose Post-Translate Simulation. The testbench for this design was setas a top level. In the menu Processes for choose ModelSim Simulator, right-click and choose Run.17ModelSim SE will be launched and waveforms for our design should appear. We can save script forfurther re-simulation by saving .do type files.There is in the bottom part ModelSim terminal. We can type there commands such like doname_of_script.do and our waveform will be updated. It is possible to use terminal in every step ofimplementation.184.4 MapGo to the menu Sources for and change this option to Synthesis/Implementation. From theImplement Design menu choose Map. Do right-click and pop-up menu should appear. Choose Run to startmapping process.194.5 Place and RouteGo to menu Sources for and change this option to Synthesis/Implementation. From the ImplementDesign menu choose Place and Route. Do right-click and pop-up menu should appear. Choose Run to startplace and route process.When we right-click on Generate Post Place and Route Simulation Model then pop-up menu appearsand you should choose204.6 Post Place and Route SimulationIn the menu Sources for we choose Post-Route Simulation. The testbench for this design was set as atop level. In the menu Processes for choose ModelSim Simulator, right-click and choose Run.ModelSim SE will be launched and waveforms for our design should appear.214.7 Implementation ReportsIn the Place & Route Report you can find final information about the amount of resources utilized andthe minimum clock period/maximum clock frequency of the design.224.8 Bit Stream GenerationGo to menu Sources for and change this option to Synthesis/Implementation. Choose GenerateProgramming File, do right-click and pop-up menu should appear. Choose Run to start bit generation process.235. Uploading Bitstream to FPGA BoardBefore uploading Bit file, make sure that you change your constant values in all your files to proper value, andre-synthesize/implement all the files. In particular, in our example, please change the value of the constantslow_clock_period in the Lab3Demo_package.vhd.Select FTU3 program as shown in the picture above. When the program is opened, a
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