FPGA Platforms High Level Language (HLL) Design FlowsResourcesSlide 3FPGA Device Capacity TrendsPrices of the most recent families of Xilinx FPGAsFPGA familiesVirtex 4Virtex-5 Family PlatformsSlide 9General Architecture of an FPGA-Based BoardReconfigurable Computing BoardsSlide 12Universal Serial Bus (USB)Digilent: BASYSDigilent: Spartan3E starter boardXilinx: Spartan3A starter kitCommon Interface - PCIEvolution of the PCI InterfaceDisadvantages of PCI & PCI-X:PCI Express (PCIe):Slide 21Slide 22Xilinx: Virtex-5 LXT/SXT/FXT ML50x Evaluation PlatformXilinx: Virtex-5 FXT ML510 Embedded Development PlatformDINI Group: DN9000K10 'Bride of Monster'FPGA Boards ConclusionsSlide 27Behavioral SynthesisNeed for High-Level DesignAdvantages of Behavioral SynthesisSlide 31Slide 32Mentor Graphics – Catapult CSlide 34Hardware-Oriented High-Level LanguagesOther High-Level Design FlowsSystemC -based design-flow alternativesSystemC EvolutionHandel-C OverviewHandel-C/ANSI-C ComparisonsHandel-C Design FlowType SummaryArraysInternal RAMs and ROMsRestrictions on RAMs and ROMsMulti-port RAMsHandel-C LanguageHandel C vs. C - functionsSlide 49Handel-C ExampleSlide 51Slide 52Slide 53Slide 54Slide 55Slide 56SRC Compilation ProcessSlide 58Slide 59Slide 60Slide 61Slide 62Slide 63Slide 64Slide 65Slide 66Slide 67Slide 68Slide 69Ideal Program EntryActual Program EntrySlide 72SummaryGeorge Mason UniversityECE 448 – FPGA and ASIC Design with VHDLFPGA PlatformsHigh Level Language (HLL)Design FlowsECE 448Lecture 212ECE 448 – FPGA and ASIC Design with VHDLResourcesUSBhttp://en.wikipedia.org/wiki/USBPCIhttp://en.wikipedia.org/wiki/PCI_Local_BusPCI-Xhttp://en.wikipedia.org/wiki/PCI-XPCIehttp://en.wikipedia.org/wiki/PCI_Express3ECE 448 – FPGA and ASIC Design with VHDLResources• Clive „Max” Maxfield, The Design Warrior’s Guide to FPGAs Chapter 11 C/C++ etc.-Based Design FlowsReconfigurable SupercomputingT. El-Ghazawi, K. Gaj, D. Buell, D. PointerTutorial at the Supercomputing 2005 conferencehttp://hpcl.seas.gwu.edu/openfpga/tutorial_html/index.html4ECE 448 – FPGA and ASIC Design with VHDLFPGA Device Capacity TrendsYear1985Xilinx Device ComplexityXC200050 MHz1K gatesXC4000100 MHz250K gatesVirtex200 MHz1M gatesVirtex-II 450 MHz8M gatesSpartan80 MHz40K gatesSpartan-II200 MHz200K gatesSpartan-3326 MHz5M gates19911987XC300085 MHz7.5K gatesVirtex-E240 MHz4M gatesXC520050 MHz23K gates1995 1998 1999 2000 2002 2003Virtex-II Pro450 MHz8M gates*2004 2006Virtex-4500 MHz16M gates*Virtex-5550 MHz24M gates*Source: http://class.ece.iastate.edu/cpre583/lectures/Lect-01.ppt5ECE 448 – FPGA and ASIC Design with VHDLPrices of the most recent families of Xilinx FPGAs Spartan 3 Virtex II, Virtex II-Pro< $130* < $3,000*Spartan 3E Virtex 4, Virtex 5 < $35* < $3,000** approximate cost of the largest device per unit for a batch of 10,000 units Low-cost High-performance6ECE 448 – FPGA and ASIC Design with VHDLFPGA familiesSpartan 3 Virtex 4 LX / SX / FXSpartan 3E Virtex 5 LX/LXT/SXT/FXT Spartan 3A Virtex 6Spartan 3ANSpartan 3A DSP Spartan 6 Low-cost High-performanceXilinxAltera Cyclone II Aria Stratix II Cyclone III Aria II Stratix II GX Stratix III L/E Stratix IV E/GX/GT7ECE 448 – FPGA and ASIC Design with VHDLVirtex 4Source: [Xilinx, Inc.]8ECE 448 – FPGA and ASIC Design with VHDLVirtex-5 Family PlatformsGeorge Mason UniversityECE 448 – FPGA and ASIC Design with VHDLFPGA Boards10ECE 448 – FPGA and ASIC Design with VHDLGeneral Architecture of an FPGA-Based BoardBUSProcessingElement(PE#0)ProcessingElement(PE#1)ProcessingElement(PE#N-1)COMMON MEMORY / INTERCONNECT NETWORKLOCALMEMORYLOCALMEMORYLOCALMEMORYCLKBUS INTERFACE CONTROLLERI/O CARD11ECE 448 – FPGA and ASIC Design with VHDLReconfigurable Computing Boards•Boards may have one or several interconnected FPGA chips•Support different bus standards, e.g. PCI, PCI-X, PCIe, USB, etc.•May have direct real-time data I/O through a daughter board•Boards may have local onboard memory (OBM) to handle large data while avoiding the system bus (e.g. PCI) bottleneck12ECE 448 – FPGA and ASIC Design with VHDL•Many boards per node can be supported•Host program (e.g. C) to interface user (and P) with a board via the board’s API•Driver API functions may include functionalities such as Reset, Open, Close, Set Clocks, DMA, Read, Write, Download Configurations, Interrupt, ReadbackReconfigurable Computing Boards13Universal Serial Bus (USB)It supports three data rates.•Full speed rate of 1.5 MB/s as defined by USB 1.0.•Low speed rate of 1.5 Mb/s which is also defined by USB 1.0. Very similar to full speed operation except that it takes each bit 8 times as long to transmit. Devices that run on the low speed rate are Keyboards, Mice and Joysticks.•High speed rate of 60 MB/s as defined by USB 2.0.Digilent: BASYS •FPGA : Spartan-3E (XC 3S100E/3S250E ) in TQ144•Price: $59 - $69•Interfaces : USB port •Memory : XCF02 Platform Flash ROM •Ethernet : None•Configuration: Device configuration through JTAG via JTAG3 parallel cable or through USB using Digilent Adept Suite software. •Applications : Academic purposes as a teaching aid in digital logic design courses.•URL: http://www.digilentinc.com/Products/Detail.cfm?Prod=BASYS&Nav1=Products&Nav2=ProgrammableDigilent: Spartan3E starter board •FPGA : Spartan-3E (XC3S500E)•Price : $149•Interfaces : USB3 port•Memory : XCF04 Platform Flash for storing FPGA configurations, 16 Mb Serial Flash, 128 Mb Strata Flash, 256 Mb DDR SDRAM •Ethernet : 10/100 Ethernet PHY•Configuration: JTAG programming via on-board USB3 port; JTAG and SPI Flash programming with parallel or JTAG USB cable•Applications : General Prototyping.•URL: http://www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Products&Nav2=ProgrammableXilinx: Spartan3A starter kit •FPGA : Spartan-3A (XC3S700A-FG484)•Price : $189•Interfaces : JTAG USB download board•Memory : 256MB DDR2 SDRAM, 32 Mb parallel Flash, 4 Mb Platform Flash PROM, 2-16 Mb SPI Flash devices •Ethernet : 10/100 Ethernet PHY•Configuration: Configuration via JTAG using USB port, Platform Flash PROM or SPI Flash Memory•Applications : General Prototyping.•URL: http://www.xilinx.com/products/devkits/HW-SPAR3A-SK-UNI-G.htm17ECE 448 – FPGA and ASIC Design with VHDLCommon Interface - PCIPCI = Peripheral Component Interconnect 32-bit bus64-bit
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