Combinational-Circuit Building Blocks Data Flow Modeling of Combinational LogicRequired readingSlide 3VHDL Design StylesSynthesizable VHDLSlide 6Slide 7SignalsMerging wires and busesSplitting busesSlide 11Slide 12Fixed Shift in VHDLFixed Rotation in VHDLSlide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Logic OperatorsNo Implied PrecedenceSlide 262-to-1 MultiplexerVHDL code for a 2-to-1 MultiplexerCascade of two multiplexersVHDL code for a cascade of two multiplexersOperatorsPriority of logic and relational operatorsVHDL operatorsSlide 34Slide 35Slide 362-to-4 DecoderVHDL code for a 2-to-4 DecoderSlide 3916-bit Unsigned AdderArithmetic Operators in VHDL (1)Arithmetic Operators in VHDL (2)VHDL code for a 16-bit Unsigned AdderSlide 444-bit Number ComparatorVHDL code for a 4-bit Unsigned Number ComparatorVHDL code for a 4-bit Signed Number ComparatorSlide 48Slide 49Slide 50Tri-state Buffer – example (1)Tri-state Buffer – example (2)Slide 53Priority EncoderVHDL code for a Priority EncoderSlide 56Slide 57MLU: Block DiagramMLU: Entity DeclarationMLU: Architecture Declarative SectionMLU - Architecture BodySlide 62Slide 63Conditional concurrent signal assignmentMost often implied structureSlide 66Selected concurrent signal assignmentMost Often Implied StructureAllowed formats of choices_kAllowed formats of choice_k - exampleGeorge Mason University ECE 448 – FPGA and ASIC Design with VHDLCombinational-Circuit Building BlocksData Flow Modeling of Combinational LogicECE 448Lecture 32 ECE 448 – FPGA and ASIC Design with VHDLRequired reading• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 6, Combinational-Circuit Building Blocks (sections 6.6.5-6.6.7 optional)Chapter 5.5, Design of Arithmetic Circuits Using CAD Tools3 ECE 448 – FPGA and ASIC Design with VHDLVHDL Design Styles4 ECE 448 – FPGA and ASIC Design with VHDLVHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowConcurrent statementsbehavioral(sequential)• Registers• State machinesSequential statementsSubset most suitable for synthesis • Testbenches5 ECE 448 – FPGA and ASIC Design with VHDLSynthesizable VHDLDataflow VHDL Design StyleVHDL codesynthesizableVHDL codesynthesizableDataflow VHDL Design Style6 ECE 448 – FPGA and ASIC Design with VHDLData-Flow VHDL• concurrent signal assignment ()• conditional concurrent signal assignment (when-else)• selected concurrent signal assignment (with-select-when)• generate scheme for equations (for-generate)Concurrent Statements7 ECE 448 – FPGA and ASIC Design with VHDLModeling Wires and Buses8 ECE 448 – FPGA and ASIC Design with VHDLSignals SIGNAL a : STD_LOGIC;SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);wireabusb189 ECE 448 – FPGA and ASIC Design with VHDLMerging wires and busesSIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL c: STD_LOGIC;SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);d <= a & b & c;4510abcd10 ECE 448 – FPGA and ASIC Design with VHDLSplitting busesSIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL c: STD_LOGIC;SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);a <= d(9 downto 6);b <= d(5 downto 1);c <= d(0);4510abcd11 ECE 448 – FPGA and ASIC Design with VHDLCombinational-CircuitBuilding Blocks12 ECE 448 – FPGA and ASIC Design with VHDLFixed Shifters & Rotators13 ECE 448 – FPGA and ASIC Design with VHDLFixed Shift in VHDLA(3)A(2)A(1)A(0)‘0’ A(3) A(2) A(1)A>>1SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL AshiftR: STD_LOGIC_VECTOR(3 DOWNTO 0);AshiftR <= AshiftRA14 ECE 448 – FPGA and ASIC Design with VHDLFixed Rotation in VHDLA(3)A(2)A(1)A(0)A(2) A(1) A(0) A(3)A<<<1SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0);ArotL <= ArotLA15 ECE 448 – FPGA and ASIC Design with VHDLGates16 ECE 448 – FPGA and ASIC Design with VHDLx 1 x 2 x n x 1 x 2 x n + + + x 1 x 2 x 1 x 2 + x 1 x 2 x n x 1 x 2 x 1 x 2 x 1 x 2 x n (a) AND gates (b) OR gatesx x (c) NOT gateBasic Gates – AND, OR, NOT17 ECE 448 – FPGA and ASIC Design with VHDLx 1 x 2 x n x 1 x 2 ¼ x n + + + x 1 x 2 x 1 x 2 + x 1 x 2 x n x 1 x 2 x 1 x 2 × x 1 x 2 ¼ x n × × × (a) NAND gates(b) NOR gates Basic Gates – NAND, NOR18 ECE 448 – FPGA and ASIC Design with VHDLx 1 x 2 x 1 x 2 x 1 x 2 x 1 x 2 x 1 x 2 x 1 x 2 x 1 x 2 x 1 x 2 + = (a) x 1 x 2 + x 1 x 2 = (b) DeMorgan’s Theorem and other symbols for NAND, NOR19 ECE 448 – FPGA and ASIC Design with VHDLBasic Gates – XOR(b) Graphical symbol(a) Truth table 0 0 1 1 0 1 0 1 0 1 1 0 x 1 x 2 x 1 x 2 f x 1 x 2 = f x 1 x 2 = (c) Sum-of-products implementationf x 1 x 2 = x 1 x 220 ECE 448 – FPGA and ASIC Design with VHDLBasic Gates – XNOR(b) Graphical symbol(a) Truth table 0 0 1 1 0 1 0 1 1 0 0 1 x 1 x 2 x 1 x 2 f x 1 x 2 = f x 1 x 2 = (c) Sum-of-products implementationf x 1 x 2 = x 1 x 2 x 1 x 2 = .21 ECE 448 – FPGA and ASIC Design with VHDLData-flow VHDL: Examplexycinscout22 ECE 448 – FPGA and ASIC Design with VHDLData-flow VHDL: Example (1)LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY fulladd ISPORT ( x : IN STD_LOGIC ; y : IN STD_LOGIC ; cin : IN STD_LOGIC ; s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ;END fulladd ;23 ECE 448 – FPGA and ASIC Design with VHDLData-flow VHDL: Example (2)ARCHITECTURE dataflow OF fulladd ISBEGINs <= x XOR y XOR cin ;cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;END dataflow ;24 ECE 448 – FPGA and ASIC Design with VHDLLogic Operators•Logic operators•Logic operators precedenceand or nand nor xor not xnor notand or nand nor xor xnorHighestLowestonly in VHDL-9325 ECE 448 – FPGA and ASIC Design with VHDL Wanted: y = ab + cdIncorrecty <= a and b or c and d ; equivalent toy <= ((a and b) or c) and d ;equivalent toy = (ab + c)dCorrecty <= (a and b) or (c and d) ;No Implied Precedence26 ECE 448 – FPGA and ASIC Design with VHDLMultiplexers27 ECE 448 – FPGA and ASIC Design with VHDL2-to-1 Multiplexer(a) Graphical symbol(b) Truth table01fsw0w1fsw0w10128 ECE 448 – FPGA and ASIC Design with VHDLVHDL code for a 2-to-1 MultiplexerLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY mux2to1 ISPORT ( w0, w1, s
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