Slide 1Required readingStructure of a Typical Digital SystemHardware Design with RTL VHDLSteps of the Design ProcessSlide 6Slide 7Circuit InterfaceInterface TableLecture 8RTL Design MethodologyMIN_MAX_AVRExample2ECE 448 – FPGA and ASIC Design with VHDLRequired reading• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 10.2, Design Examples• P. Chu, FPGA Prototyping by VHDL Examples Chapter 6, FSMDStructure of a Typical Digital SystemDatapath(Execution Unit)Controller(Control Unit)Data InputsData OutputsControl InputsControl OutputsControl SignalsStatusSignalsHardware Design with RTL VHDLPseudocodeDatapath ControllerBlockdiagramBlockdiagramState diagramor ASM chartVHDL code VHDL code VHDL codeInterfaceSteps of the Design Process1. Text description2. Interface3. Pseudocode4. Block diagram of the Datapath5. Interface with the division into the Datapath and the Controller6. ASM chart of the Controller7. RTL VHDL code8. Testbench9. Debugging10. Synthesis and implementation11. Experimental testingSteps of the Design Process1. Text description2. Interface3. Pseudocode4. Block diagram of the Datapath5. Interface with the division into the Datapath and the Controller6. ASM chart of the Controller7. RTL VHDL code8. Testbench9. Debugging10. Synthesis and implementation11. Experimental testingMIN_MAX_AVRExampleCircuit Interfacen5n2clkresetin_datain_addrwriteSTARTDONEout_dataout_addrMIN_MAX_AVRInterface TablePort Width Meaningclk 1 System clockreset 1 System reset – clears internal registersin_data n Input data busin_addr 5 Address of the internal memory where input data is storedwrite 1 Synchronous write control signalSTART 1 Starts the computationsDONE 1 Asserted when all results are readyout_data n Output data bus used to read resultsout_addr 2 01 – reading minimum10 – reading maximum11 – reading
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