Slide 1Slide 2MLU Block DiagramSlide 4PicoBlaze OverviewSlide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Block diagramSlide 24FunctionInterfaceSlide 27Fixed Shifts in VHDLArithmetic Functions in VHDL (1)Arithmetic Functions in VHDL (2)ECE 448 – FPGA and ASIC Design with VHDL George Mason UniversityECE 448: Lab 1Review of Aldec Active HDL Implementing Combinational Logic in VHDLExample: MLUPart 1Introduction to Aldec Active-HDLMLU Block DiagramBANEG_ANEG_BIN0IN1IN2IN3OUTPUTSEL1SEL0MUX_4_1L0L1NEG_YYY1A1B1MUX_0MUX_1MUX_2MUX_3010101Experiment 1Problem 1ALU of PicoBlazePicoBlaze OverviewRegister File of PicoBlaze01777000Address7 07 07 07 07 016 Registers8-bit7 0Fs0s1s2s3s4s5s6s7234567sFCondition Code Registers (Flags) and its DefinitionZ = 1 if result = 0 0 otherwiseZero flag - Zzero conditionExample*C = 1 if result > 28-1 or result < 0 0 otherwise*Applies only to addition or subtraction related instructions, refer to following slides otherwiseCarry flag - Coverflow, underflow, or various conditionsFlags are set or reset after ALU operationsSyntax and TerminologySyntax Example DefinitionsXkkPORT(kk)PORT((sX))RAM(kk)s1514PORT(2)PORT((S10))RAM(4)Value at register 15Value 14Input value from port 2Input value from port specified by register 10Value from RAM location 4Addressing modesDirect modeINPUT s10, 28ADD s10, s15PORT(28) s10s10 + s15 s10Indirect modeINPUT s9, s2STORE s3, s10PORT((s2)) s9 s3 RAM((s10)) s2 + 15 + C s2s7 – 7 s7Immediate modeADDCY s2, 15SUB s7, 7Assembly language vs. machine codeAssembly languagemnemonic [operands] ADDCY s2, 16SUB s7, s8Machine code*1A 2, 10 1A2101C 7, 8 1C780opcode [operands] instruction*Value in HEXLogic instructions1. ANDAND sX, sYsX & sY => sXAND sX, kk sX & kk => sX2. OROR sX, sYsX & sY => sXOR sX, kk sX & kk => sX3. XORXOR sX, sYsX & sY => sXXOR sX, kk sX & kk => sXIMM, DIRC ZIMM, DIRIMM, DIRArithmetic Instructions1. Addition1.1 ADD sX, sY sX + sY => sX ADD sX, kk sX + kk => sX1.2 ADDCY sX, sY sX + sY + CARRY => sX ADDCY sX, kk sX + kk + CARRY => sX2. Subtraction2.1 SUB sX, sY sX - sY => sX SUB sX, kk sX - kk => sX2.2 SUBCY sX, sY sX - sY - CARRY => sX SUBCY sX, kk sX - kk - CARRY => sXIMM, DIRC ZIMM, DIRTest and Compare InstructionsTEST TEST sX, sYsX & sY => none TEST sX, kksX & kk => noneCOMPARE COMPARE sX, sYsX – sY => none COMPARE sX, kksX – kk => noneC ZIMM, DIRIMM, DIRData Movement Instructions (1)LOAD LOAD sX, sYsY => sX LOAD sX, kkkk => sXSTORE STORE sX, PPsX => RAM(PP) STORE sX, (sY)sX => RAM((sY))FETCH FETCH sX, PPRAM(PP) => sX FETCH sX, (sY)RAM((sY)) => sX IMM, DIRDIR, INDC Z- -- -- -DIR, INDData Movement Instructions (2)INPUT INPUT sX, PPsY => PORT(PP) INPUT sX, (sY)sX => PORT((sY))OUTPUT OUTPUT sX, PPPORT(PP) => sX OUTPUT sX, (sY)PORT((sY)) => sXDIR, INDDIR, INDC Z- -- -Edit instructions - Shifts*All shift instructions affect Zero and Carry flagsEdit instructions - Rotations*All rotate instructions affect Zero and Carry flagsPicoBlaze ALU Instruction Set Summary (1)Instruction 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0ADD sX, kk 0 1 1 0 0 0 x x x x y y y y 0 0 0 0ADD sX, sY 0 1 1 0 0 1 x x x x k k k k k k k kADDCY sX, kk 0 1 1 0 1 0 x x x x y y y y 0 0 0 0ADDCY sX, sY 0 1 1 0 1 1 x x x x k k k k k k k kAND sX, kk 0 0 1 0 1 0 x x x x y y y y 0 0 0 0AND sX, sY 0 0 1 0 1 1 x x x x k k k k k k k kCOMPARE sX, kk 0 1 0 1 0 0 x x x x y y y y 0 0 0 0COMPARE sX, sY 0 1 0 1 0 1 x x x x k k k k k k k kFETCH sX, ss 0 0 0 1 1 0 x x x x 0 0 s s s s s sFETCH sX, (sY) 0 0 0 1 1 1 x x x x y y y y 0 0 0 0INPUT sX, (sY) 0 0 0 1 0 1 x x x x y y y y 0 0 0 0INPUT sX, PP 0 0 0 1 0 0 x x x x p p p p p p p pLOAD sX, kk 0 0 0 0 0 0 x x x x k k k k k k k kLOAD sX, sY 0 0 0 0 0 1 x x x x y y y y 0 0 0 0OR sX, kk 0 0 1 1 0 0 x x x x k k k k k k k kOR sX, sY 0 0 1 1 0 1 x x x x y y y y 0 0 0 0OUTPUT sX, (sY) 1 0 1 1 0 1 x x x x y y y y 0 0 0 0OUTPUT sX, PP 1 0 1 1 0 0 x x x x p p p p p p p pPicoBlaze ALU Instruction Set Summary (2)Instruction 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RL sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 0 1 0RR sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 0 0SL0 sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 1 1 0SL1 sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 1 1 1SLA sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 0 0 0SLX sX 1 0 0 0 0 0 x x x x 0 0 0 0 0 1 0 0SR0 sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 1 0SR1 sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 1 1 1SRA sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 0 0 0SRX sX 1 0 0 0 0 0 x x x x 0 0 0 0 1 0 1 0STORE sX, ss 1 0 1 1 1 0 x x x x 0 0 s s s s s sSTORE sX, (sY) 1 0 1 1 1 1 x x x x y y y y 0 0 0 0SUB sX, kk 0 1 1 1 0 0 x x x x k k k k k k k kSUB sX, sY 0 1 1 1 0 1 x x x x y y y y 0 0 0 0SUBCY sX, kk 0 1 1 1 1 0 x x x x k k k k k k k kSUBCY sX, sY 0 1 1 1 1 1 x x x x y y y y 0 0 0 0TEST sX, kk 0 1 0 0 1 0 x x x x k k …
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