ECE 448 FPGA and ASIC Design with VHDLSlide 2Slide 3Slide 4Slide 5Slide 6ECE 448 Lab Section Preference FormSlide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Levels of design descriptionRegister Transfer Logic (RTL) Design DescriptionVHDL Design StylesTestbenchesWorld of Integrated CircuitsSlide 22Slide 23FPGA Design process (1)FPGA Design process (2)Simulation ToolsSlide 27Slide 28Synthesis ToolsSlide 30ImplementationSlide 32Slide 33Top Level ASIC Digital Design FlowSlide 35Slide 36Slide 37XESS Inc. Educational BoardsSlide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45ECE 448 FPGA and ASIC Design with VHDLSpring 2006ECE 448 TeamCourse Instructor: Kris Gaj [email protected], [email protected] Instructors (TAs):Monday & Wednesday section: Hoang LeMS CpE student, specializing inDigital Systems [email protected] & Thursday section:Ramakrishna BachimanchiMS CpE student, specializing inDigital Systems [email protected] 448 Team – Division of TasksCourse Instructor – Primary Responsibilities- Lectures- Preparing and grading exams- Instructions for the labs & development of new experiments- Coordination of work done by the TAs- Enforcing consistent policies and grading standards- Mid-semester student satisfaction survey- Resolving conflicts and providing feedback to the TAs- Holding office hoursECE 448 Team – Division of TasksLab Instructors (TAs) – Primary Responsibilities- Teaching hands-on sessions on how to use software, hardware and testing equipment needed for experiments- Introductions to the lab experiments- Grading student demonstrations and reports- Helping in the preparation of new experiments- Holding office hoursCourse hoursLecture: Tuesday, Thursday 5:55-7:10 PM, S&T 2, room 15Lab Sessions: Monday, Tuesday, Wednesday, Thursday 7:20-10:00 PM, S&T 2, room 203Office hours:Monday, 3:00-4:00 PM, room 203, Hoang LeTuesday, 4:00-5:00 PM, room 203, Ramakrishna BachimanchiTuesday, 4:30-5:30 PM, room 223, Kris GajWednesday, 5:00-6:00 PM, room 203, Hoang LeThursday, 4:00-5:00 PM, room 203, Ramakrishna BachimanchiThursday, 7:30-8:30 PM, room 223, Kris Gaj• You are welcome to attend any of the multiple office hour sessions• Please attend the class meetings of the other section only in case of emergency and give preference in access to the lab computers to the students attending the right section• All experiment demonstrations and report submissions need to be done in the presence of your TA, and can be done exclusively during the class time of your sectionECE 448 Section Assignment RulesECE 448 Lab Section Preference FormFirst Name: KevinLast Name: Smith Preferred Possible Impossible Monday, Section 201 7:20-10:00 PM TA: Hoang Le Tuesday, Section 202 7:20-10:00 PM TA: Ramakrishna Bachimanchi Wednesday, Section 203 7:20-10:00 PM TA: Hoang Le Thursday, Section 204 7:20-10:00 PM TA: Ramakrishna Bachimanchi• Please clearly mark your preferences on the distributed form or return your form blank• All changes in assignments to a particular lab section will be determined by Friday, January 27, and sent to you by e-mail• You do NOT need to do anything to move to the right section• All assignments are FINAL and cannot be changed in the middle of the semesterSection Preference FormLab Access Rules and Behavior CodePlease refer to the FPGA Design & Test Lab website:http://ece.gmu.edu/labs/fpgalab.htmGrading criteriaFirst part of the semester (before the Spring break)Second part of the semester (after the Spring break)Lab experiments & homework - Part I(individual assignments)25%Final exam25%Lab experiments & homework - Part II (group assignments)25%Midterm exam for the lecture: 10%Midterm exam for the lab: 15%ECE 331ECE 332ECE 280 CECE 445 CECE 442ECE 447 C CECE 448Digital Systems & ComputersPHYS 261 PHYS 262orTransition from ECE 449 to ECE 448ECE 4491 credit hourVHDL intro+ FPGA intro+ hands-on tools intro+ experiment intro+ lab time4 credit hoursLectureLabNEW COURSE, ECE 448 VHDL intro+ FPGA intro+ ASIC intro+ more advancedlectures on applications and platformshands-on tools intro+ experiment intro+ lab timeLabVHDL: - writing synthesizable RTL level code in VHDL - writing test benchesFPGAs: - architecture of FPGA devices - tools for the computer-aided design with FPGAs - current FPGA families & future trendsTopicsECE 448, FPGA and ASIC Design with VHDLApplications: - basics of computer arithmetic - applications from communications, digital signal processing, and cryptography- FPGA boards- microprocessor board–FPGA board interfaces: PCI, PCI-X- reconfigurable computersHigh-level ASIC Design: - standard cell implementation approach - logic synthesis tools - differences between FPGA & standard-cell ASIC design flowNew trends:- using high-level programming languages to design hardware- microprocessors embedded in FPGAsPlatforms:Tasks of the courseAdvancedcourse on digitalsystem designwith VHDLComprehensive introduction toFPGA & front-end ASICtechnologyTesting equipment- writing VHDL code for synthesis- design using finite state machines and algorithmic state machines- test benches- hardware: Xilinx FPGAs,TSMC libraryof standard ASICcells- software:VHDL simulatorsSynthesis toolsXilinx ISE- oscilloscopes- logic analyzerVHDL for SpecificationVHDL for SimulationVHDL for SynthesisLevels of design descriptionAlgorithmic levelRegister Transfer LevelLogic (gate) levelCircuit (transistor) levelPhysical (layout) levelLevel of description most suitable for synthesisRegister Transfer Logic (RTL) Design Description Combinational Logic Combinational LogicRegisters…VHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowConcurrent statementsbehavioral• Registers• State machines• Test benchesSequential statementsSubset most suitable for synthesisTestbenchesTestbench EnvironmentTB ProcessesGeneratingStimuli Design Under Test (DUT)Stimuli All DUT Inputs Simulated OutputsWorld of Integrated CircuitsIntegrated CircuitsFull-CustomASICsSemi-CustomASICsUserProgrammablePLD FPGAPAL PLA PMLLUT(Look-Up Table)MUX Gates• designs must be sent for expensive and time consuming fabrication in semiconductor foundry• bought off the shelf and reconfigured by designers themselvesTwo competing implementation approachesASICApplication SpecificIntegrated CircuitFPGAField
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