DOC PREVIEW
MASON ECE 448 - Lecture 6 Mixing Design Styles

This preview shows page 1-2-17-18-19-35-36 out of 36 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 36 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 36 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 36 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 36 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 36 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 36 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 36 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 36 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

Mixing Design Styles Synthesis Modeling of circuits with regular structureSlide 2VHDL Design StylesMixed Style ModelingPRNG Example (1)PRNG Example (2)SynthesisResources & Required ReadingDesign flow (1)Synthesis ToolsSlide 11Features of synthesis toolsTiming report after synthesisSlide 14Slide 15Slide 16Example 1A 4-to-1 MultiplexerStraightforward code for Example 1Slide 20Modified code for Example 1Slide 22Example 2A 2-to-4 binary decoderVHDL code for Example 2 (1)VHDL code for Example 2 (2)Slide 27Example 3: Variable rotator - InterfaceBlock diagramVHDL code for a 16-bit 2-to-1 MultiplexerFixed rotationFixed rotation by L positionsVHDL code for for a fixed 16-bit rotatorStructural VHDL code for for a variable 16-bit rotator (1)Structural VHDL code for for a variable 16-bit rotator (2)Structural VHDL code for for a variable 16-bit rotator (3)George Mason University ECE 448 – FPGA and ASIC Design with VHDLMixing Design StylesSynthesis Modeling of circuits with regularstructureECE 448Lecture 62 ECE 448 – FPGA and ASIC Design with VHDLMixing Design Styles Inside of an Architecture3 ECE 448 – FPGA and ASIC Design with VHDLVHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowConcurrent statementsbehavioral• Registers• Shift registers• Counters• State machinesSequential statementssynthesizable4 ECE 448 – FPGA and ASIC Design with VHDLarchitecture ARCHITECTURE_NAME of ENTITY_NAME is •Here you can declare signals, constants, functions, procedures…•Component declarations•No variable declarations !!beginConcurrent statements:•Concurrent simple signal assignment •Conditional signal assignment •Selected signal assignment•Generate statement•Component instantiation statement•Process statement•inside process you can use only sequential statementsend ARCHITECTURE_NAME;Mixed Style ModelingConcurrent Statements5 ECE 448 – FPGA and ASIC Design with VHDLPRNG Example (1)library IEEE;use IEEE.STD_LOGIC_1164.all; use work.prng_pkg.all;ENTITY PRNG ISPORT( Coeff : in std_logic_vector(4 downto 0);Load_Coeff : in std_logic; Seed : in std_logic_vector(4 downto 0); Init_Run : in std_logic; Clk : in std_logic; Current_State : out std_logic_vector(4 downto 0));END PRNG;ARCHITECTURE mixed OF PRNG issignal Ands : std_logic_vector(4 downto 0);signal Sin : std_logic;signal Coeff_Q : std_logic_vector(4 downto 0);signal Shift5_Q : std_logic_vector(4 downto 0);6 ECE 448 – FPGA and ASIC Design with VHDLPRNG Example (2)-- Data FlowG: FOR I IN 0 TO 4 GENERATEAnds(I) <= Coeff_Q(I) AND Shift5_Q(I);END GENERATE;Sin <= Ands(0) XOR Ands(1) XOR Ands(2) XOR Ands(3) XOR Ands(4);Current_State <= Shift5_Q;-- BehavioralCoeff_Reg: PROCESS(Clk)BEGINIF Clk'EVENT and Clk = '1' THENIF Load_Coeff = '1' THENCoeff_Q <= Coeff;END IF;END IF;END PROCESS; -- Structural Shift5_Reg : Shift5 PORT MAP ( D => Seed, Load => Init_Run, Sin => Sin, Clock => Clk, Q => Shift5_Q);END mixed;George Mason University ECE 448 – FPGA and ASIC Design with VHDLSynthesis8 ECE 448 – FPGA and ASIC Design with VHDLResources & Required ReadingIntegrated Interfaces: Active-HDL with Synplify®Integrated Synthesis and ImplementationMovie DemosActive-HDL Help9 ECE 448 – FPGA and ASIC Design with VHDLDesign flow (1)Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; );end AES_core;Specification (Lab Experiments)VHDL description (Your Source Files)Functional simulationPost-synthesis simulationSynthesis10 ECE 448 – FPGA and ASIC Design with VHDLSynthesis Tools… and othersSynplify ProXilinx XST11 ECE 448 – FPGA and ASIC Design with VHDLarchitecture MLU_DATAFLOW of MLU issignal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;beginA1<=A when (NEG_A='0') elsenot A;B1<=B when (NEG_B='0') elsenot B;Y<=Y1 when (NEG_Y='0') elsenot Y1;MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;with (L1 & L0) selectY1<=MUX_0 when "00",MUX_1 when "01",MUX_2 when "10",MUX_3 when others;end MLU_DATAFLOW;VHDL descriptionCircuit netlistLogic Synthesis12 ECE 448 – FPGA and ASIC Design with VHDLFeatures of synthesis tools•Interpret RTL code•Produce synthesized circuit netlist in a standard EDIF format•Give preliminary performance estimates•Display circuit schematic corresponding to EDIF netlist13 ECE 448 – FPGA and ASIC Design with VHDLTiming report after synthesisPerformance Summary *******************Worst slack in design: -0.924 Requested Estimated Requested Estimated Starting Clock Frequency Frequency Period Period Slack-------------------------------------------------------------------------------------------------------System 85.0 MHz 86.4 MHz 11.765 11.572 0.193 ===========================================================Slack = Estimated Clock Period – Requested Clock PeriodNegative Slack means timing violationsPositive Slack means positive margin before timing violation14 ECE 448 – FPGA and ASIC Design with VHDLGenerate schemefor components15 ECE 448 – FPGA and ASIC Design with VHDLStructural VHDL• component instantiation (port map)• component instantiation with generic (generic map, port map)• generate scheme for component instantiations (for-generate)Major instructions16 ECE 448 – FPGA and ASIC Design with VHDLExample 117 ECE 448 – FPGA and ASIC Design with VHDLw 8 w 11s 1 w 0 s 0 w 3 w 4 w 7 w 12w 15s 3 s 2 f Example 118 ECE 448 – FPGA and ASIC Design with VHDLA 4-to-1 MultiplexerLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY mux4to1 ISPORT ( w0, w1, w2, w3 : IN STD_LOGIC ;s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;f : OUT STD_LOGIC ) ;END mux4to1 ;ARCHITECTURE Dataflow OF mux4to1 ISBEGINWITH s SELECTf <= w0 WHEN


View Full Document

MASON ECE 448 - Lecture 6 Mixing Design Styles

Documents in this Course
Load more
Download Lecture 6 Mixing Design Styles
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Lecture 6 Mixing Design Styles and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Lecture 6 Mixing Design Styles 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?