Experiment 7 VHDL Modeling of Embedded Microprocessors and MicrocontrollersSimple MicroprocessorBasic ArchitectureInstruction CyclesArchitectural ConsiderationsA Simple (Trivial) Instruction SetAddressing ModesSample ProgramArchitecture of a Simple MicroprocessorA Simple MicroprocessorPIC MicrocontrollerPIC Microcontroller implemented inside of an FPGA deviceSlide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Questions?ECE 448 – FPGA and ASIC Design with VHDL George Mason UniversityExperiment 7VHDL Modeling of Embedded Microprocessors and MicrocontrollersECE 448 – FPGA and ASIC Design with VHDL George Mason UniversitySimple MicroprocessorECE 448 – FPGA and ASIC Design with VHDL 3Basic Architecture•Control unit and datapath•Note similarity to single-purpose processor•Key differences•Datapath is general•Control unit doesn’t store the algorithm – the algorithm is “programmed” into the memoryProcessorControl unit DatapathALURegistersIRPCControllerMemoryI/OControl/StatusSource: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"ECE 448 – FPGA and ASIC Design with VHDL 4Instruction CyclesProcessorControl unit DatapathALURegistersIRPCController MemoryI/OControl/Status10......load R0, M[500]500501100inc R1, R0101store M[501], R1102R0 R1PC=10010Fetch opsExec.Store resultsclkFetchload R0, M[500]Decode100Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"ECE 448 – FPGA and ASIC Design with VHDL 5Architectural Considerations•Clock frequency•Inverse of clock period•Must be longer than longest register to register delay in entire processor•Memory access is often the longestProcessorControl unit DatapathALURegistersIRPCControllerMemoryI/OControl/StatusSource: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"ECE 448 – FPGA and ASIC Design with VHDL 6A Simple (Trivial) Instruction Set opcode operandsMOV Rn, directMOV @Rn, RmADD Rn, Rm0000 Rn direct0010 Rn0100 RmRnRn = M(direct)Rn = Rn + RmSUB Rn, Rm 0101 Rm Rn = Rn - RmMOV Rn, #immed. 0011 Rn immediate Rn = immediateAssembly instruct. First byte Second byte OperationJZ Rn, relative 0110 Rn relativePC = PC+ relative (only if Rn is 0)RnMOV direct, Rn 0001 Rn direct M(direct) = RnRmM(Rn) = RmSource: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"ECE 448 – FPGA and ASIC Design with VHDL 7Addressing ModesDataImmediateRegister-directRegisterindirectDirectIndirectDataOperand fieldRegister addressRegister addressMemory addressMemory addressMemory address DataDataMemory addressDataAddressingmodeRegister-filecontentsMemorycontentsSource: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"ECE 448 – FPGA and ASIC Design with VHDL 8Sample Programint total = 0;for (int i=10; i!=0; i--) total += i;// next instructions...C programMOV R0, #0; // total = 0MOV R1, #10; // i = 10JZ R1, Next; // Done if i=0ADD R0, R1; // total += iMOV R2, #1; // constant 1JZ R3, Loop; // Jump alwaysLoop:Next: // next instructions...SUB R1, R2; // i--Equivalent assembly programMOV R3, #0; // constant 00123567Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"ECE 448 – FPGA and ASIC Design with VHDL 9Architecture of a Simple Microprocessor•Storage devices for each declared variable•register file holds each of the variables•Functional units to carry out the FSMD operations•One ALU carries out every required operation•Connections added among the components’ ports corresponding to the operations required by the FSM •Unique identifiers created for every control signalDatapathIRPCController(Next-state and controllogic; state register)MemoryRF (16)RFwaRFweRFr1aRFr1eRFr2aRFr2eRFr1 RFr2RFwALUALUs2x1 muxALUzRFsPCldPCincPCclr3x1 muxMsMweMreTo all input control signalsFrom all output control signalsControl unit16Irld210AD10Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"ECE 448 – FPGA and ASIC Design with VHDL 10A Simple MicroprocessorFSM operations that replace the FSMD operations after a datapath is createdRFwa=rn; RFwe=1; RFs=01;Ms=01; Mre=1;RFr1a=rn; RFr1e=1; Ms=01; Mwe=1;RFr1a=rn; RFr1e=1; Ms=00; Mwe=1;RFwa=rn; RFwe=1; RFs=10;RFwa=rn; RFwe=1; RFs=00;RFr1a=rn; RFr1e=1;RFr2a=rm; RFr2e=1; ALUs=00RFwa=rn; RFwe=1; RFs=00;RFr1a=rn; RFr1e=1;RFr2a=rm; RFr2e=1; ALUs=01PCld= ALUz;RFrla=rn;RFrle=1;MS=10;Irld=1;Mre=1;PCinc=1;PCclr=1;ResetFetchDecodeIR=M[PC];PC=PC+1Mov1RF[rn] = M[dir]Mov2Mov3Mov4AddSubJz011001010100001100100001op = 0000M[dir] = RF[rn]M[rn] = RF[rm]RF[rn]= immRF[rn] =RF[rn]+RF[rm]RF[rn] = RF[rn]-RF[rm]PC=(RF[rn]=0) ?rel :PCto Fetchto Fetchto Fetchto Fetchto Fetchto Fetchto FetchPC=0;from states belowFSMDDatapathIRPCController(Next-state and controllogic; state register)MemoryRF (16)RFwaRFweRFr1aRFr1eRFr2aRFr2eRFr1 RFr2RFwALUALUs2x1 muxALUzRFsPCldPCincPCclr3x1 muxMsMweMreTo all input control signalsFrom all output control signalsControl unit16Irld210AD10You just built a simple microprocessor!Source: Vahid and Givargis, "Embedded System Design: A Unified Hardware/Software Introduction"ECE 448 – FPGA and ASIC Design with VHDL George Mason UniversityPIC MicrocontrollerECE 448 – FPGA and ASIC Design with VHDL 12PIC Microcontroller implemented inside of an FPGA devicePICµControllerFPGAPORTBPORTA7-Seg DecoderPORTADisplayPORTC= PORTC(0)STROBECLKRESETECE 448 – FPGA and ASIC Design with VHDL 13PICROM256 x 12DataAddrPROGRAMPCInstruction DecoderWALUCOMPUTATIONS8124CONSTANTSOPCODESAddress BusData Bus88CONTROL UNITMCLR CLKEXTENDEDALUPORTA PORTB PORTC4 8 8DATAFSRDin DoutREGFILER8R31Fsel48 88PIC Microcontroller CoreECE 448 – FPGA and ASIC Design with VHDL 14Set Port DirectionsRESETSum <= ‘0’Counter <= ‘0’Wait for a rising edge at Port C(0)Port B <= Port ASum <= Sum + Port ACounter <= Counter + 1Counter = 8?NYWait for a rising edge at Port C(0)Port B <= Sum(3 downto 0)Wait for a rising edge at Port C(0)Port B <= Sum(7 downto 4)Flowchart of our PIC programECE 448 – FPGA and ASIC Design with VHDL 15Selected Registers of PICWPCPORTAADDRWorking Register (Accumulator)Program CounterPORTBPORTC0506070809R8R9R30R311FBidirectional Input/Output PortsRegister File (General Purpose
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