Structural Design Style Behavioral Design Style: Registers and CountersRequired readingOptional ReadingRegister Transfer Level (RTL) Design DescriptionSlide 5VHDL Design StylesSlide 7Slide 8Circuit built of medium scale components2-to-1 MultiplexerVHDL code for a 2-to-1 MultiplexerPriority EncoderVHDL code for a Priority Encoder2-to-4 DecoderVHDL code for a 2-to-4 DecoderSlide 16Structural description – example (1)Structural description – example (2)Structural description – example (3)Named association connectivityPositional association connectivityStructural description with positional association connectivitySlide 23Package – example (1)Package – example (2)Package usage (1)Package usage (2)Slide 28Configuration declarationConfiguration specificationSlide 31Slide 32Example 1A 4-to-1 MultiplexerStraightforward code for Example 1Slide 36Modified code for Example 1Slide 38Variable rotator - InterfaceBlock diagramVHDL code for a 16-bit 2-to-1 MultiplexerFixed rotationVHDL code for for a fixed 16-bit rotatorStructural VHDL code for for a variable 16-bit rotator (1)Structural VHDL code for for a variable 16-bit rotator (2)Structural VHDL code for for a variable 16-bit rotator (3)Slide 47What is a PROCESS?Anatomy of a ProcessStatement PartPROCESS with a SENSITIVITY LISTProcesses in VHDLSlide 53Component Equivalent of a ProcessSlide 55Slide 56Slide 57Slide 58Slide 59Slide 60Slide 61Slide 62Slide 63Slide 64Slide 65Slide 66Slide 67Slide 68Slide 69Slide 70Slide 71Shift registerShift Register With Parallel LoadSlide 74Slide 75Slide 76Slide 77George Mason University ECE 448 – FPGA and ASIC Design with VHDLStructural Design StyleBehavioral Design Style: Registers and Counters ECE 448Lecture 42 ECE 448 – FPGA and ASIC Design with VHDLRequired reading• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 6, Combinational-Circuit Building Blocks (sections 6.6.5-6.6.7 optional)Chapter 5.5, Design of Arithmetic Circuits Using CAD ToolsChapter 7, Flip-Flops, Registers, Counters, and a Simple Processor (7.14 optional)3 ECE 448 – FPGA and ASIC Design with VHDLOptional Reading• Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 3, Gates, Decoders and Encoders Chapter 4, Registers and Latches (see errata at http://www.vahana.com/bugs.htm)4 ECE 448 – FPGA and ASIC Design with VHDLRegister Transfer Level (RTL) Design Description Combinational Logic Combinational LogicRegisters…5 ECE 448 – FPGA and ASIC Design with VHDLStructural Design Style6 ECE 448 – FPGA and ASIC Design with VHDLVHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowConcurrent statementsbehavioral• Registers & countersSequential statements7 ECE 448 – FPGA and ASIC Design with VHDLStructural VHDL• component instantiation (port map)• generate scheme for component instantiations (for-generate)• component instantiation with generic (generic map, port map)Major instructions8 ECE 448 – FPGA and ASIC Design with VHDLStructural VHDL• component instantiation (port map)• generate scheme for component instantiations (for-generate)• component instantiation with generic (generic map, port map)Major instructions9 ECE 448 – FPGA and ASIC Design with VHDLCircuit built of medium scale componentsw 0 w 3 y 0 y 1 z w 1 w 2 w 0 Eny 0 w 1 y 1 y 2 y 3 s(0)01s(1)01r(0)r(1)r(2)r(3)r(4)r(5)p(0)p(1)p(2)p(3)q(0)q(1)enaz(0)z(1)z(2)z(3)dec2to4priority10 ECE 448 – FPGA and ASIC Design with VHDL2-to-1 Multiplexer(a) Graphical symbol(b) Truth table01fsw0w1fsw0w10111 ECE 448 – FPGA and ASIC Design with VHDLVHDL code for a 2-to-1 MultiplexerLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY mux2to1 ISPORT ( w0, w1, s : IN STD_LOGIC ;f : OUT STD_LOGIC ) ;END mux2to1 ;ARCHITECTURE dataflow OF mux2to1 ISBEGINf <= w0 WHEN s = '0' ELSE w1 ;END dataflow ;12 ECE 448 – FPGA and ASIC Design with VHDLPriority Encoderd001010w0y1dy01 101111z1xx0xw101x0xw20010xw300001w 0 w 3 y 0 y 1 z w 1 w 213 ECE 448 – FPGA and ASIC Design with VHDLVHDL code for a Priority EncoderLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY priority ISPORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC ) ;END priority ;ARCHITECTURE dataflow OF priority ISBEGINy <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE"01" WHEN w(1) = '1' ELSE"00" ;z <= '0' WHEN w = "0000" ELSE '1' ;END dataflow ;14 ECE 448 – FPGA and ASIC Design with VHDL2-to-4 Decoder0 0 1 1 1 0 1 y 0 w 1 0 w 0 x x 1 1 0 1 1 En0 0 0 1 0 y 1 1 0 0 0 0 y 2 0 1 0 0 0 y 3 0 0 1 0 0 w 0 Eny 0 w 1 y 1 y 2 y 3 (a) Truth table (b) Graphical symbol15 ECE 448 – FPGA and ASIC Design with VHDLVHDL code for a 2-to-4 DecoderLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;END dec2to4 ;ARCHITECTURE dataflow OF dec2to4 ISSIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;BEGINEnw <= En & w ;WITH Enw SELECTy <= "1000" WHEN "100","0100" WHEN "101","0010" WHEN "110","0001" WHEN "111","0000" WHEN OTHERS ;END dataflow ;16 ECE 448 – FPGA and ASIC Design with VHDLCircuit built of medium scale componentsw 0 w 3 y 0 y 1 z w 1 w 2 w 0 Eny 0 w 1 y 1 y 2 y 3 s(0)01s(1)01r(0)r(1)r(2)r(3)r(4)r(5)p(0)p(1)p(2)p(3)q(0)q(1)enaz(0)z(1)z(2)z(3)dec2to4priority17 ECE 448 – FPGA and ASIC Design with VHDLStructural description – example (1)LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY priority_resolver ISPORT (r : IN STD_LOGIC_VECTOR(5 DOWNTO 0) ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; z : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;END priority_resolver;ARCHITECTURE structural OF priority_resolver ISSIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ;SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ;SIGNAL ena : STD_LOGIC ;18 ECE 448 – FPGA and ASIC Design with VHDLStructural description – example (2)COMPONENT mux2to1PORT (w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ;END COMPONENT ;COMPONENT priorityPORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC ) ;END COMPONENT ;COMPONENT dec2to4PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;END COMPONENT ;19 ECE 448 – FPGA and ASIC Design with VHDLStructural description – example (3) BEGIN u1: mux2to1 PORT MAP (w0 => r(0) , w1 =>
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