MASON ECE 448 - Tutorial on Hardware and Software Design Flow Based on PicoBlaze Microcontroller (11 pages)

Previewing pages 1, 2, 3, 4 of 11 page document View the full content.
View Full Document

Tutorial on Hardware and Software Design Flow Based on PicoBlaze Microcontroller



Previewing pages 1, 2, 3, 4 of actual document.

View the full content.
View Full Document
View Full Document

Tutorial on Hardware and Software Design Flow Based on PicoBlaze Microcontroller

86 views

Problems/Exams


Pages:
11
School:
George Mason University
Course:
Ece 448 - FPGA and ASIC Design with VHDL
FPGA and ASIC Design with VHDL Documents

Unformatted text preview:

Tutorial on Hardware and Software Design Flow Based on PicoBlaze Microcontroller with Celoxica RC10 development board ver 1 0 1 Prepared by Marcin Rogawski Ekawat Ice Homsirikamol and Dr Kris Gaj The current version of the tutorial was tested using the following tools CAD Tool Xilinx ISE Webpack Version 9 1 Synthesis Tool ISE Webpack Synthesis Implementation Version 9 1 Synplicity Synplify Pro Version 8 6 Implementation Tool Xilinx ISE WebPack Version 9 1 FPGA Board Celoxica RC10 Xilinx JTAG Parallel III Cable Microcontroller Xilinx PicoBlaze Software Development Tools Xilinx KCPSM3 Assembler Xilinx JTAG LOADER 2 1 Introduction to Design Flow of a System with PicoBlaze When you complete this tutorial you will be able to perform Hardware and Software Combined Separated Design Flow with Xilinx PicoBlaze 3 1 1 Hardware and Software Combined Design Flow A PicoBlaze KCPSM3 program is stored in a BRAM configured as a ROM The program is normally modified by a change to the configuration bit stream The KCPSM3 assembler reads a VHDL or Verilog template describing the BRAM configuration and simply adds the initialization strings to define the program KCPSM3 as an input is taking ROM form and psm files First file is a template of Instruction memory and second is assembler design file The PSM program is assembled and the resulting VHDL or Verilog file is included in the design This is then processed through the normal ISE tools and used to configure the device via USB cable Celoxica FTU3 software 4 1 2 Hardware and Software Separated Design Flow Replace your ROM form vhd template by JTAG Loader ROM form vhd This adds a few slices of logic to connect the second port of the BRAM to the JTAG controller inside the FPGA It also adds a reset control Assemble your code to create new vhdl and hex file Add the reset to the instantiation of the program ROM and connect to the PicoBlaze Implement new design and configure your FPGA by new bitstream Chapter 3 contains more details Once you



View Full Document

Access the best Study Guides, Lecture Notes and Practice Exams

Loading Unlocking...
Login

Join to view Tutorial on Hardware and Software Design Flow Based on PicoBlaze Microcontroller and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Tutorial on Hardware and Software Design Flow Based on PicoBlaze Microcontroller and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?