1"" Tutorial on Hardware and Software Design Flow Based on PicoBlaze Microcontroller with Celoxica RC10 development board ver. 1.02"" Prepared by Marcin Rogawski, Ekawat (Ice) Homsirikamol, and Dr. Kris Gaj The current version of the tutorial was tested using the following tools: CAD Tool Xilinx ISE Webpack Version : 9.1 Synthesis Tool ISE&Webpack Synthesis&Implementation Version : 9.1 Synplicity Synplify Pro Version : 8.6 Implementation Tool Xilinx ISE/WebPack Version : 9.1 FPGA Board Celoxica RC10 Xilinx JTAG Parallel III Cable Microcontroller Xilinx PicoBlaze Software Development Tools: Xilinx KCPSM3 Assembler Xilinx JTAG_LOADER3"" 1. Introduction to Design Flow of a System with PicoBlaze When you complete this tutorial you will be able to perform Hardware and Software Combined/Separated Design Flow with Xilinx PicoBlaze.4"" 1.1. Hardware and Software Combined Design Flow A PicoBlaze (KCPSM3) program is stored in a BRAM configured as a ROM. The program is normally modified by a change to the configuration bit stream. The KCPSM3 assembler reads a VHDL or Verilog template describing the BRAM configuration and simply adds the initialization strings to define the program. KCPSM3 as an input is taking ROM_form and *.psm files. First file is a template of Instruction memory and second is assembler design file. The PSM program is assembled and the resulting VHDL (or Verilog) file is included in the design. This is then processed through the normal ISE tools and used to configure the device via USB cable (Celoxica FTU3 software).5"" 1.2. Hardware and Software Separated Design Flow Replace your ROM_form.vhd template by JTAG_Loader_ROM_form.vhd. This adds a few slices of logic to connect the second port of the BRAM to the JTAG controller inside the FPGA. It also adds a reset control. Assemble your code to create new vhdl and hex file. Add the ‘reset’ to the instantiation of the program ROM and connect to the PicoBlaze. Implement new design and configure your FPGA by new bitstream. Chapter 3 contains more details. Once you configure your hardware you can easily modify your assembly code and update software only. Chapter 4 contains procedure of software update.6""2. Hardware Settings for JTAG The JTAG interface is under the plastic transparent cover. First you have to unscrew this cover. Connect JTAG cable to the parallel port in your PC and to the board JTAG connector.7"" Use Celoxica FTU3 software to configure your FPGA. The Bitstream should contain: - PicoBlaze instantiation, - JTAG hardware driver - Initial software (stored in instruction memory)8""3. JTAG Chain initialization by iMPACT We have to initialize JTAG chain before we start software update procedure. Click Start->Xilinx Ise Design Suite XX.Y-> ISE->Accessories->iMPACT. You should see main window of Xilinx iMPACT. Click on Boundary Scan.9""New white window appear inside of iMPACT main window. Right click to Initialize JTAG chain.10"" If everything is fine with connection with the board you should see your FPGA in Boundary Scan window. JTAG Chain is successfully initialized. You can close iMPACT software. If you are not successful with this step probably you didn’t connect JTAG cable properly to the board.11"" 4. Software Update Start Microsoft Windows shell. Type “jtag_loader.bat” with the name of hex file as an input argument (Remember that file name should be without extension). Press “Enter” and you should see SUCCESS – Completed XSVF execution. It means that new version of software was successfully updated. Check new functionality of your software working in the PicoBlaze
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