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MASON ECE 448 - Introduction to FPGA board & FPGA Implementation Tools

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Introduction to FPGA board & FPGA Implementation ToolsFPGA Design FlowDesign flow (1)Design flow (2)SynthesisSynthesis ToolsSlide 7ImplementationSlide 9Implementation (cont)TranslationSample UCF FilePin AssignmentConstraints EditorCircuit netlistMappingPlacingRoutingConfigurationSlide 20Static Timing AnalyzerStatic Timing AnalysisSlide 23Timing Characteristics of Combinational CircuitsTiming Characteristics of Combinational Circuits (2)Timing Characteristics of Combinational Circuits (3)Timing Characteristics of Combinational Circuits (4)Slide 28Timing vs. functional simulationSDF fileNetlist from the synthesis toolCeloxica RC10 FPGA BoardSlide 33Slide 34Slide 35Slide 36Slide 37Slide 38Piezo BuzzerSlide 40Slide 41Slide 42Hands-on SessionQuestions?ECE 449 – Computer Design Lab George Mason UniversityIntroduction toFPGA board& FPGA Implementation ToolsECE 449 – Computer Design Lab George Mason UniversityFPGA Design FlowECE 449 – Computer Design Lab 3Design flow (1)Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; );end AES_core;Specification (Lab Experiments)VHDL description (Your Source Files)Functional simulationPost-synthesis simulationSynthesisECE 449 – Computer Design Lab 4Design flow (2)ImplementationConfigurationTiming simulationOn chip testingECE 449 – Computer Design Lab George Mason UniversitySynthesisECE 449 – Computer Design Lab 6Synthesis Tools… and othersSynplify ProXilinx XSTECE 449 – Computer Design Lab 7architecture MLU_DATAFLOW of MLU issignal A1:STD_LOGIC;signal B1:STD_LOGIC;signal Y1:STD_LOGIC;signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;beginA1<=A when (NEG_A='0') elsenot A;B1<=B when (NEG_B='0') elsenot B;Y<=Y1 when (NEG_Y='0') elsenot Y1;MUX_0<=A1 and B1;MUX_1<=A1 or B1;MUX_2<=A1 xor B1;MUX_3<=A1 xnor B1;with (L1 & L0) selectY1<=MUX_0 when "00",MUX_1 when "01",MUX_2 when "10",MUX_3 when others;end MLU_DATAFLOW;VHDL descriptionCircuit netlistLogic SynthesisECE 449 – Computer Design Lab George Mason UniversityImplementationECE 449 – Computer Design Lab 9Implementation•After synthesis the entire implementation process is performed by FPGA vendor toolsECE 449 – Computer Design Lab 10Implementation (cont)ECE 449 – Computer Design Lab 11TranslationTranslationUCFNGDEDIFNCFNative Generic Database fileConstraint EditorUser Constraint FileNative Constraint FileElectronic Design Interchange FormatCircuit netlist Timing ConstraintsSynthesisECE 449 – Computer Design Lab 12Sample UCF FileNET "clock" LOC = "P8";NET "control<0>" LOC = "K4";NET "control<1>" LOC = "K3";NET "control<2>" LOC = "K2";NET "reset" LOC = "E11";NET "segments<0>" LOC = "R10";NET "segments<1>" LOC = "P10";NET "segments<2>" LOC = "M11";NET "segments<3>" LOC = "M6";NET "segments<4>" LOC = "N6";NET "segments<5>" LOC = "T7";NET "segments<6>" LOC = "R7";ECE 449 – Computer Design Lab 13Pin AssignmentLAB2CLOCKCONTROL(0)CONTROL(2)CONTROL(1)RESETSEGMENTS(0)SEGMENTS(1)SEGMENTS(2)SEGMENTS(3)SEGMENTS(4)SEGMENTS(5)SEGMENTS(6)P10K2N6K3R7K4T7M6M11R10P8E11FPGAECE 449 – Computer Design Lab 14Constraints EditorECE 449 – Computer Design Lab 15Circuit netlistECE 449 – Computer Design Lab 16MappingLUT2LUT3LUT4LUT5LUT1FF1FF2LUT0ECE 449 – Computer Design Lab 17PlacingCLB SLICESFPGAECE 449 – Computer Design Lab 18RoutingProgrammable ConnectionsFPGAECE 449 – Computer Design Lab 19Configuration•Once a design is implemented, you must create a file that the FPGA can understand•This file is called a bit stream: a BIT file (.bit extension)•The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming informationECE 449 – Computer Design Lab 20Static Timing AnalysisECE 449 – Computer Design Lab 21Static Timing Analyzer•Performs static analysis of the circuit performance•Reports critical paths with all sources of delays•Determines maximum clock frequencyECE 449 – Computer Design Lab 22Static Timing Analysis•Critical Path – The Longest Path From Outputs of Registers to Inputs of RegistersD QinclkD QouttP logictCritical = tP FF + tP logic + tS FFECE 449 – Computer Design Lab 23Static Timing Analysis•Min. Clock Period = Length of The Critical Path•Max. Clock Frequency = 1 / Min. Clock PeriodECE 449 – Computer Design Lab 24Timing Characteristics of Combinational Circuits•Combinational Circuits Are Characterized by Propagation Delays•through logic components (gates, LUTs)•through interconnects (routing delays)tp LUTtp routingLUT LUT LUTTotal propagation delay through combinational logicECE 449 – Computer Design Lab 25Timing Characteristics of Combinational Circuits (2)•Total Propagation Delay of Logic Depends on the Number of Logic Levels and Delays of Logic Components•Number of logic levels is the number of logic components (gates, LUTs) the signal propagates through•Routing Delays Depend on:•Length of interconnects•FanoutECE 449 – Computer Design Lab 26Timing Characteristics of Combinational Circuits (3)•Fanout – Number of Inputs Connected to One Output•Each inputs has its capacitance•Fast switching of outputs with high fanout requires higher currents and strong driversLUT LUTLUTLUTECE 449 – Computer Design Lab 27Timing Characteristics of Combinational Circuits (4)In Current FPGAs Routing Delaystypically account for 45% to 65% of thetotal path delaysECE 449 – Computer Design Lab 28Timing simulation after implementationECE 449 – Computer Design Lab 29Timing vs. functional simulation• Simulation before synthesis is used to verify circuit functionality and may differ from the one after synthesis and implementation• Implementation tool generates SDF (Standard Delay Format) as a standard delay file and the netlist for synthesized VHDL code with delays.• Generated netlist contains many component instantiation statements with library referencesECE 449 – Computer Design Lab 30SDF file( DELAYFILE ( CELL(


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