Midterm ExamECE 448Spring 2008Tuesday Section(15 points)InstructionsZip all your deliverables into an archive <last_name>.zip and submit it through WebCTno later than Tuesday, March 4, 10:00 PM EST.IntroductionDesign a system that performs a bit-serial multiplication of two 4-bit unsigned numbers.The algorithm begins when the input START is set to a ‘1’. When the algorithm iscomplete, a DONE signal goes high, indicating the completion of the multiplication.The pseudocode for the multiplication algorithm is shown below:A_Reg = A_INB_Reg = 0For i in 0 to 7 loopIf I < 4B_Reg = B_Reg[2:0] & B_IN (i); -- Least significant bit first.ElseB_Reg = B_Reg [2:0] & ‘0’For j in 3 downto 0 loopIf j == 3Sum(j) = (A_Reg(j)) and B_Reg(j)) xor Previous_Carry(j)Carry(j) = A_Reg(j) and B_Reg(j) and Previous_Carry(j)Previous_Carry(j) = Carry(j)ElseSum(j) = (A_Reg(j) and B_Reg(j)) xor Previous_Carry(j) xorSum(j+1)Carry(j) = Majority ((A_Reg(j) and B_Reg(j)), Previous_Carry(j),Sum(j+1))Previous_Carry(j) = Carry(j)End if;End loop;End loop;The interface circuit is shown below:MultiplyCLOCKRESETA_INB_INSTART4RESULTDONESignalNameType Size FunctionCLOCK Input 1 20 ns, 50% duty cycle clockRESET Input 1 Reset signalA_IN Input 4 Multiplicand A, parallel inputB_IN Input 1 Multiplier B, serial input starting from LSB and endingwith MSBSTART Input 1 Starts the computation algorithm, high for one clock cycleRESULT Output 1 Serial output of result, starting with LSB and ending withMSBDONE Output 1 Signals the end of computationThe execution unit for the circuit is shown below. Note that all inputs that are in capitalletters are external inputs. Inputs that are written with lowercase letters are inputs from acontrol unit.The timing waveforms for two successive computations are shown below:Design RequirementsThe combinational portion of the circuit should be described using the dataflow VHDLcode, and the sequential portion of the circuit should be described using the synthesizablebehavioral code. Your code should infer a circuit that requires a minimum amount ofFPGA resources.TasksPerform the following tasks:1. Write a VHDL code of the execution unit of the described above circuit (shown in theblock diagram above).2. Write a testbench verifying the operation of your execution unit.3. Perform functional simulation of your circuit and use it to debug your VHDL code.4. Design a control unit of your circuit. If you do not know how to do it, go to Step 6.5. Write a testbench verifying the operation of your entire code.6. Synthesize your circuit and save the RTL schematic.7. Implement your circuit.8. Perform timing simulations of your circuit.9. Run the static timing analysis of your circuit.10. Based on the circuit block diagram and the implementation reports, determine themost critical path in your circuit and its length.Deliverables1. VHDL code of your entire circuit fulfilling the requirements specified in the DesignRequirements section above2. VHDL code of your testbenches3. RTL schematic of your circuit4. Timing waveforms from the functional simulation demonstrating the correct operationof your circuit.5. Description of the critical path in your circuit6. Timing waveforms from the timing simulation demonstrating the delay of the circuitmost critical path7. FPGA resource utilization8. Minimum clock period of your
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