Finite State MachinesRequired readingOptional ReadingSlide 4Structure of a Typical Digital SystemExecution Unit (Datapath)Control Unit (Control)Slide 8Finite State Machines (FSMs)Moore FSMMealy FSMMoore MachineMealy MachineMoore vs. Mealy FSM (1)Moore vs. Mealy FSM (2)Moore FSM - Example 1Mealy FSM - Example 1Moore & Mealy FSMs – Example 1Slide 19FSMs in VHDLSlide 21Slide 22Slide 23Moore FSM in VHDL (1)Moore FSM in VHDL (2)Slide 26Mealy FSM in VHDL (1)Mealy FSM in VHDL (2)Slide 29Slide 30Slide 31Slide 32Slide 33Moore FSM – Example 2: VHDL code (3)Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Mealy FSM – Example 2: VHDL code (2)Mealy FSM – Example 2: VHDL code (3)Slide 44State Encoding ProblemTypes of State Encodings (1)Types of State Encodings (2)Slide 48Slide 49George Mason University ECE 448 – FPGA and ASIC Design with VHDLFinite State Machines ECE 448Lecture 82 ECE 448 – FPGA and ASIC Design with VHDLRequired reading• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 8, Synchronous Sequential Circuits Sections 8.1-8.53 ECE 448 – FPGA and ASIC Design with VHDLOptional Reading• Sundar Rajan, Essential VHDL: RTL Synthesis Done RightChapter 6, Finite State Machines4 ECE 448 – FPGA and ASIC Design with VHDLExecution Unitvs.Control Unit5 ECE 448 – FPGA and ASIC Design with VHDLStructure of a Typical Digital SystemExecution Unit(Datapath)Control Unit(Control)Data InputsData OutputsControl InputsControl OutputsControl Signals6 ECE 448 – FPGA and ASIC Design with VHDLExecution Unit (Datapath)•Provides All Necessary Resources and Interconnects Among Them to Perform Specified Task•Examples of Resources•Adders, Multipliers, Registers, Memories, etc.7 ECE 448 – FPGA and ASIC Design with VHDLControl Unit (Control)•Controls Data Movements in the Execution Unit by Switching Multiplexers and Enabling or Disabling Resources•Follows Some ‘Program’ or Schedule•Often Implemented as Finite State Machine or collection of Finite State Machines8 ECE 448 – FPGA and ASIC Design with VHDLFinite State MachinesRefresher9 ECE 448 – FPGA and ASIC Design with VHDLFinite State Machines (FSMs)•Any Circuit with Memory Is a Finite State Machine•Even computers can be viewed as huge FSMs•Design of FSMs Involves•Defining states•Defining transitions between states•Optimization / minimization•Manual Optimization/Minimization Is Practical for Small FSMs Only10 ECE 448 – FPGA and ASIC Design with VHDLMoore FSM•Output Is a Function of a Present State OnlyPresent StateregisterNext StatefunctionOutputfunctionInputsPresent StateNext StateOutputsclockreset11 ECE 448 – FPGA and ASIC Design with VHDLMealy FSM•Output Is a Function of a Present State and InputsNext StatefunctionOutputfunctionInputsPresent StateNext StateOutputsPresent Stateregisterclockreset12 ECE 448 – FPGA and ASIC Design with VHDLMoore Machinestate 1 /output 1state 2 /output 2transitioncondition 1transitioncondition 213 ECE 448 – FPGA and ASIC Design with VHDLMealy Machinestate 1state 2transition condition 1 /output 1transition condition 2 /output 214 ECE 448 – FPGA and ASIC Design with VHDLMoore vs. Mealy FSM (1)•Moore and Mealy FSMs Can Be Functionally Equivalent•Equivalent Mealy FSM can be derived from Moore FSM and vice versa•Mealy FSM Has Richer Description and Usually Requires Smaller Number of States•Smaller circuit area15 ECE 448 – FPGA and ASIC Design with VHDLMoore vs. Mealy FSM (2)•Mealy FSM Computes Outputs as soon as Inputs Change•Mealy FSM responds one clock cycle sooner than equivalent Moore FSM•Moore FSM Has No Combinational Path Between Inputs and Outputs•Moore FSM is more likely to have a shorter critical path16 ECE 448 – FPGA and ASIC Design with VHDLMoore FSM - Example 1•Moore FSM that Recognizes Sequence “10”S0 / 0 S1 / 0 S2 / 1000111resetMeaning of states:S0: No elements of the sequenceobservedS1: “1”observedS2: “10”observed17 ECE 448 – FPGA and ASIC Design with VHDLMealy FSM - Example 1•Mealy FSM that Recognizes Sequence “10”S0 S10 / 01 / 0 1 / 00 / 1resetMeaning of states:S0: No elements of the sequenceobservedS1: “1”observed18 ECE 448 – FPGA and ASIC Design with VHDLMoore & Mealy FSMs – Example 1clockinputMooreMealy0 1 0 0 0S0 S1 S2 S0 S0S0 S1 S0 S0 S019 ECE 448 – FPGA and ASIC Design with VHDLFinite State Machinesin VHDL20 ECE 448 – FPGA and ASIC Design with VHDLFSMs in VHDL•Finite State Machines Can Be Easily Described With Processes•Synthesis Tools Understand FSM Description If Certain Rules Are Followed•State transitions should be described in a process sensitive to clock and asynchronous reset signals only•Outputs described as concurrent statements outside the process21 ECE 448 – FPGA and ASIC Design with VHDLMoore FSMPresent StateRegisterNext StatefunctionOutputfunctionInputsPresent StateNext StateOutputsclockresetprocess(clock, reset)concurrent statements22 ECE 448 – FPGA and ASIC Design with VHDLMealy FSMNext StatefunctionOutputfunctionInputsPresent StateNext StateOutputsPresent StateRegisterclockresetprocess(clock, reset)concurrent statements23 ECE 448 – FPGA and ASIC Design with VHDLMoore FSM - Example 1•Moore FSM that Recognizes Sequence “10”S0 / 0 S1 / 0 S2 / 1000111reset24 ECE 448 – FPGA and ASIC Design with VHDLMoore FSM in VHDL (1)TYPE state IS (S0, S1, S2);SIGNAL Moore_state: state;U_Moore: PROCESS (clock, reset)BEGINIF(reset = ‘1’) THENMoore_state <= S0;ELSIF (clock = ‘1’ AND clock’event) THENCASE Moore_state ISWHEN S0 => IF input = ‘1’ THEN Moore_state <= S1; ELSE Moore_state <= S0; END IF;25 ECE 448 – FPGA and ASIC Design with VHDLMoore FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF; WHEN S2 => IF input = ‘0’ THEN Moore_state <= S0; ELSE Moore_state <= S1; END IF;END CASE;END IF;END PROCESS;Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’;26 ECE 448 – FPGA and ASIC Design with VHDLMealy FSM - Example 1•Mealy FSM that Recognizes Sequence “10”S0 S10 / 01 / 0 1 / 00 / 1reset27 ECE 448 – FPGA and ASIC Design with VHDLMealy FSM in VHDL (1)TYPE state IS (S0, S1);SIGNAL Mealy_state: state;U_Mealy: PROCESS(clock, reset)BEGINIF(reset = ‘1’) THENMealy_state <= S0;ELSIF (clock = ‘1’
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