VHDL RefresherRequired readingRecommended readingSlide 4Slide 5VHDLGenesis of VHDLA Brief History of VHDLFour versions of VHDLSlide 10VerilogVHDL vs. VerilogSlide 13Features of VHDL and VerilogSlide 15Naming and Labeling (1)Naming and Labeling (2)Valid or invalid?Free FormatReadability standardsCommentsSlide 22Slide 23Example: NAND GateExample VHDL CodeDesign EntityEntity DeclarationEntity declaration – simplified syntaxPort Mode INPort Mode OUTPort Mode OUT (with extra signal)Port Mode BUFFERPort Mode INOUTPort Modes - SummaryArchitectureArchitecture – simplified syntaxEntity Declaration & ArchitectureSlide 38Slide 39Slide 40Library DeclarationsLibrary declarations - syntaxFundamental parts of a libraryLibrariesSlide 45STD_LOGICBIT versus STD_LOGICSTD_LOGIC type demystifiedMore on STD_LOGIC Meanings (1)More on STD_LOGIC Meanings (2)Slide 51More on STD_LOGIC Meanings (4)Resolving logic levelsSTD_LOGIC RulesSlide 55SignalsStandard Logic VectorsVectors and ConcatenationFixed Rotation in VHDLFixed Shift in VHDLSlide 61VHDL Design StylesSlide 63Entity xor3Dataflow Architecture (xor3 gate)Dataflow DescriptionStructural Architecture (xor3 gate)xor2Structural DescriptionBehavioral Architecture (xor3 gate)Behavioral Description?ECE 448 – FPGA and ASIC Design with VHDL George Mason UniversityVHDL RefresherLecture 2ECE 448 – FPGA and ASIC Design with VHDL 2Required reading• M. Zwolinski, Digital System Design with VHDLChapter 3, Combinational logic using VHDL gate modelsChapter 4, Combinational building blocks• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 2.10, Introduction to VHDLECE 448 – FPGA and ASIC Design with VHDL 3Recommended reading• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 5.5.4, Arithmetic Assignment StatementsAdditional material required during the first lab experimentECE 448 – FPGA and ASIC Design with VHDL 4Recommended reading• Wikipedia – The Free On-line Encyclopedia VHDL - http://en.wikipedia.org/wiki/VHDL Verilog - http://en.wikipedia.org/wiki/VerilogECE 448 – FPGA and ASIC Design with VHDL 5Brief History of VHDLECE 448 – FPGA and ASIC Design with VHDL 6VHDL•VHDL is a language for describing digital hardware used by industry worldwide•VHDL is an acronym for VHSIC (Very High Speed Integrated Circuit) Hardware Description LanguageECE 448 – FPGA and ASIC Design with VHDL 7Genesis of VHDL•Multiple design entry methods and hardware description languages in use•No or limited portability of designs between CAD tools from different vendors•Objective: shortening the time from a design concept to implementation from 18 months to 6 monthsState of art circa 1980ECE 448 – FPGA and ASIC Design with VHDL 8A Brief History of VHDL•June 1981: Woods Hole Workshop•July 1983: contract awarded to develop VHDL•Intermetrics•IBM•Texas Instruments•August 1985: VHDL Version 7.2 released•December 1987: VHDL became IEEE Standard 1076-1987 and in 1988 an ANSI standardECE 448 – FPGA and ASIC Design with VHDL 9Four versions of VHDL•Four versions of VHDL:•IEEE-1076 1987•IEEE-1076 1993 most commonly supported by CAD tools•IEEE-1076 2000 (minor changes)•IEEE-1076 2002 (minor changes)ECE 448 – FPGA and ASIC Design with VHDL 10VerilogECE 448 – FPGA and ASIC Design with VHDL 11Verilog•Essentially identical in function to VHDL•No generate statement•Simpler and syntactically different•C-like•Gateway Design Automation Co., 1985•Gateway acquired by Cadence in 1990•IEEE Standard 1364-1995•Early de facto standard for ASIC programming•Programming language interface to allow connection to non-Verilog codeECE 448 – FPGA and ASIC Design with VHDL 12 VHDL vs. VerilogGovernment DevelopedCommercially DevelopedAda based C basedStrongly Type Cast Mildly Type CastCase-insensitive Case-sensitiveDifficult to learn Easier to LearnMore Powerful Less PowerfulECE 448 – FPGA and ASIC Design with VHDL 13How to learn Verilog by yourself ?ECE 448 – FPGA and ASIC Design with VHDL 14Features of VHDL and Verilog•Technology/vendor independent•Portable•ReusableECE 448 – FPGA and ASIC Design with VHDL 15VHDL FundamentalsECE 448 – FPGA and ASIC Design with VHDL 16Naming and Labeling (1)•VHDL is case insensitiveExample:Names or labelsdatabusDatabusDataBusDATABUSare all equivalentECE 448 – FPGA and ASIC Design with VHDL 17Naming and Labeling (2)General rules of thumb (according to VHDL-87)1. All names should start with an alphabet character (a-z or A-Z)2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)3. Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)4. Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid)5. All names and labels in a given entity and architecture must be uniqueECE 448 – FPGA and ASIC Design with VHDL 18Valid or invalid?7segment_displayA87372477424Adder/Subtractor/resetAnd_or_gateAND__OR__NOTKogge-Stone-AdderRipple&Carry_AdderMy adderECE 448 – FPGA and ASIC Design with VHDL 19Free Format•VHDL is a “free format” language No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way.Example:if (a=b) thenorif (a=b) then orif (a =b) thenare all equivalentECE 448 – FPGA and ASIC Design with VHDL 20Readability standardsESA VHDL Modelling Guidelinespublished byEuropean Space Research and Technology Centerin September 1994available at the course web pageECE 448 – FPGA and ASIC Design with VHDL 21Comments•Comments in VHDL are indicated with a “double dash”, i.e., “--”Comment indicator can be placed anywhere in the lineAny text that follows in the same line is treated as a commentCarriage return terminates a commentNo method for commenting a block extending over a couple of linesExamples:-- main subcircuitData_in <= Data_bus; -- reading data from the input FIFOECE 448 – FPGA and ASIC Design with VHDL 22Comments•Explain Function of Module to Other Designers•Explanatory, Not Just Restatement of Code•Locate Close to Code Described•Put near executable code, not just in a headerECE 448 – FPGA and ASIC Design with VHDL 23Design EntityECE 448 – FPGA and ASIC Design with VHDL 24Example: NAND Gatea b z0 0 10 1 11 0 11 1 0abzECE 448 – FPGA and ASIC Design with VHDL 25Example VHDL Code•3
View Full Document
Unlocking...