Slide 1SourcesSimple TestbenchAdvanced TestbenchSlide 5Slide 6Slide 7AssertAssert - syntaxAssert - ExamplesReport - syntaxReport - ExamplesSlide 13Slide 14RecordsSlide 16Variable – Example (1)Variable – Example (2)Variables - featuresSlide 20Testbench (1)Testbench (2)Testbench (3)Testbench (4)Testbench (5)Slide 26Design Under Test (1)Design Under Test (2)Test vector file (1)Test vector file (2)Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Testbench (6)Testbench (7)Hex formatGeorge Mason University ECE 448 – FPGA and ASIC Design with VHDLECE 448Lecture 13Advanced Testbenches2 ECE 448 – FPGA and ASIC Design with VHDLSources•Sundar Rajan, Essential VHDL: RTL Synthesis Done RightChapter 14, starting from “Design Verification” (handout distributed in class)3 ECE 448 – FPGA and ASIC Design with VHDLSimple TestbenchProcessesGeneratingInputStimuli Design Under Test (DUT)Outputs Observedas Timing Waveforms4 ECE 448 – FPGA and ASIC Design with VHDLAdvanced TestbenchProcessesGeneratingInputStimuli Design Under Test (DUT)ProcessComparingActual Outputsvs.Expected OutputsDesignCorrect/IncorrectYes/No5 ECE 448 – FPGA and ASIC Design with VHDLSourceofRepresentativeInputsVHDL DesignManual CalculationsorReference Software Implementation(C, Java, Matlab )Expected OutputsActual Outputs= ?InputsPossible Sources of Expected Outputs6 ECE 448 – FPGA and ASIC Design with VHDLTest vectorsSet of pairs: {Input i, Expected Output i}Input 1, Expected Output 1Input 2, Expected Output 2……………………………Input N, Expected Output NTest vectors can be: - defined in the testbench source file - stored in a data file7 ECE 448 – FPGA and ASIC Design with VHDLAsserts & Reports8 ECE 448 – FPGA and ASIC Design with VHDLAssertAssert is a non-synthesizable statementwhose purpose is to write out messageson the screen when problems are foundduring simulation.Depending on the severity of the problem,The simulator is instructed to continuesimulation or halt.9 ECE 448 – FPGA and ASIC Design with VHDLAssert - syntaxASSERT condition[REPORT "message"[SEVERITY severity_level ];The message is written when the condition is FALSE.Severity_level can be: Note, Warning, Error (default), or Failure.10 ECE 448 – FPGA and ASIC Design with VHDLAssert - Examplesassert initial_value <= max_value report "initial value too large" severity error;assert packet_length /= 0 report "empty network packet received" severity warning;assert false report "Initialization complete" severity „note”;11 ECE 448 – FPGA and ASIC Design with VHDLReport - syntaxREPORT "message"[SEVERITY severity_level ];The message is always written.Severity_level can be: Note (default), Warning, Error, or Failure.12 ECE 448 – FPGA and ASIC Design with VHDLReport - Examplesreport "Initialization complete";report "Current time = " & time'image(now);report "Incorrect branch" severity error;13 ECE 448 – FPGA and ASIC Design with VHDLlibrary IEEE;use IEEE.STD_LOGIC_1164.all;entity example_1_tb isend example_1_tb;architecture behavioral of example_1_tb issignal clk : std_logic := '0';begin clk <= not clk after 100 ns;processbeginwait for 1000 ns;report "Initialization complete";report "Current time = " & time'image(now); wait for 1000 ns;report "SIMULATION COMPLETED" severity failure;end process;end behavioral;Report - Examples14 ECE 448 – FPGA and ASIC Design with VHDLRecords15 ECE 448 – FPGA and ASIC Design with VHDLRecordstype opcodes is (add, sub, and, or);type reg_number is range 0 to 8;type instruction is recordopcode : opcodes;source_reg1 : reg_number;source_reg2 : reg_number;dest_reg : reg_number;end record instruction;constant add_instr_1_3 : instruction:=(opcode => add, source_reg1 | dest_reg => 1, source_reg2 => 3);16 ECE 448 – FPGA and ASIC Design with VHDLVariables17 ECE 448 – FPGA and ASIC Design with VHDLVariable – Example (1)LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY Numbits ISPORT ( X : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; Count : OUT INTEGER RANGE 0 TO 16) ;END Numbits ;18 ECE 448 – FPGA and ASIC Design with VHDLVariable – Example (2)ARCHITECTURE Behavior OF Numbits ISBEGINPROCESS(X) – count the number of bits in X equal to 1VARIABLE Tmp: INTEGER;BEGIN Tmp := 0; FOR i IN 15 DOWNTO 0 LOOP IF X(i) = ‘1’ THEN Tmp := Tmp + 1; END IF; END LOOP; Count <= Tmp;END PROCESS;END Behavior ;19 ECE 448 – FPGA and ASIC Design with VHDLVariables - features•Can only be declared within processes and subprograms (functions & procedures)•Initial value can be explicitly specified in the declaration•When assigned take an assigned value immediately•Variable assignments represent the desired behavior, not the structure of the circuit•Should be avoided, or at least used with caution in a synthesizable code20 ECE 448 – FPGA and ASIC Design with VHDLUsing Arrays of Test VectorsIn Testbenches21 ECE 448 – FPGA and ASIC Design with VHDLTestbench (1)LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY sevenSegmentTB isEND sevenSegmentTB;ARCHITECTURE testbench OF sevenSegmentTB ISCOMPONENTsevenSegment PORT ( bcdInputs : IN STD_LOGIC_VECTOR (3 DOWNTO 0); seven_seg_outputs : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); );end COMPONENT;CONSTANT PropDelay: time := 40 ns;CONSTANT SimLoopDelay: time := 10 ns;22 ECE 448 – FPGA and ASIC Design with VHDLTestbench (2)TYPE vector IS RECORD bcdStimulus: STD_LOGIC_VECTOR(3 downto 0); sevSegOut: STD_LOGIC_VECTOR(6 downto 0);END RECORD;CONSTANT NumVectors: INTEGER:= 10;TYPE vectorArray is ARRAY (0 TO NumVectors - 1) OF vector;CONSTANT vectorTable: vectorArray := ( (bcdStimulus => "0000", sevSegOut => "0000001"), (bcdStimulus => "0001", sevSegOut => "1001111"), (bcdStimulus => "0010", sevSegOut => "0010010"), (bcdStimulus => "0011", sevSegOut => "0000110"), (bcdStimulus => "0100", sevSegOut => "1001100"), (bcdStimulus => "0101", sevSegOut => "0100100"), (bcdStimulus => "0110", sevSegOut => "0100000"), (bcdStimulus => "0111", sevSegOut => "0001111"), (bcdStimulus => "1000", sevSegOut => "0000000"), (bcdStimulus => "1001", sevSegOut => "0000100"));23 ECE 448 – FPGA and ASIC Design with VHDLTestbench (3)SIGNAL StimInputs: STD_LOGIC_VECTOR(3 downto 0);SIGNAL CaptureOutputs: STD_LOGIC_VECTOR(6 downto 0);BEGIN u1: sevenSegment PORT MAP (bcdInputs => StimInputs,seven_seg_outputs => CaptureOutputs);24 ECE 448 – FPGA and ASIC Design with VHDLTestbench (4)LoopStim: PROCESSBEGIN FOR i in 0 TO
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