VHDL Coding for SynthesisRequired readingOptional ReadingSlide 4DelaysInitializationsReports and assertsFloating-point operationsSlide 9Register Transfer Level (RTL) Design DescriptionVHDL Design StylesSlide 12Slide 13Slide 14Slide 15Slide 16Arithmetic operationsSlide 18Operations on Unsigned NumbersOperations on Signed NumbersSigned and Unsigned TypesInteger TypesSlide 23Addition of Signed Numbers (1)Addition of Signed Numbers (2)Addition of Signed Numbers (3)Addition of Unsigned NumbersMultiplication of signed and unsigned numbers (1)Multiplication of signed and unsigned numbers (2)Slide 30Describing combinational logic using processesSlide 32Slide 33Incorrect code for combinational logic - Implied latch (1)Incorrect code for combinational logic - Implied latch (2)Slide 36Covering all cases in the IF statementCovering all cases in the CASE statementSlide 39Advanced VHDL for synthesisN-bit NANDN-bit NAND architecture using variablesIncorrect N-bit NAND architecture using signalsCorrect N-bit NAND architecture using signalsParity generator entityParity generator architecture using signalsParity generator architecture using variablesSlide 48For BeginnersSlide 50For IntermmediatesFor Intermmediates (2)Slide 53For AdvancedGeorge Mason University ECE 448 – FPGA and ASIC Design with VHDLVHDL Coding for SynthesisECE 448Lecture 102 ECE 448 – FPGA and ASIC Design with VHDLRequired reading• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 6, Combinational-Circuit Building Blocks (sections 6.6.5-6.6.8)Chapter 5.5, Design of Arithmetic Circuits Using CAD Tools• S. Lee, Advanced Digital Logic Design, Chapter 4.4, Synthesis Heuristics (handout)3 ECE 448 – FPGA and ASIC Design with VHDLOptional Reading• Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 5, Counters and Simple Arithmetic Functions4 ECE 448 – FPGA and ASIC Design with VHDLNon-synthesizable VHDL5 ECE 448 – FPGA and ASIC Design with VHDLDelaysDelays are not synthesizableStatements, such as wait for 5 ns a <= b after 10 nswill not produce the required delay, and should not be used in the code intendedfor synthesis.6 ECE 448 – FPGA and ASIC Design with VHDLInitializationsDeclarations of signals (and variables)with initialized values, such as SIGNAL a : STD_LOGIC := ‘0’;cannot be synthesized, and thus shouldbe avoided.If present, they will be ignored by thesynthesis tools. Use set and reset signals instead.7 ECE 448 – FPGA and ASIC Design with VHDLReports and assertsReports and asserts, such as report "Initialization complete"; assert initial_value <= max_value report "initial value too large" severity error;cannot be synthesized, but theycan be freely used in the code intended forsynthesis.They will be used during simulation andignored during synthesis.8 ECE 448 – FPGA and ASIC Design with VHDLFloating-point operationsOperations on signals (and variables)of the type realare not synthesizable by the current generation of synthesis tools.9 ECE 448 – FPGA and ASIC Design with VHDLSynthesizable VHDL10 ECE 448 – FPGA and ASIC Design with VHDLRegister Transfer Level (RTL) Design Description Combinational Logic Combinational LogicRegisters…11 ECE 448 – FPGA and ASIC Design with VHDLVHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowConcurrent statementsbehavioral• Registers• Shift registers• Counters• State machinesSequential statementsand moreif you are carefulsynthesizable12 ECE 448 – FPGA and ASIC Design with VHDLCombinational Logic Synthesisfor Beginners13 ECE 448 – FPGA and ASIC Design with VHDL• concurrent signal assignment ()• conditional concurrent signal assignment (when-else)• selected concurrent signal assignment (with-select-when)• generate scheme for equations (for-generate)Simple rules for beginnersFor combinational logic,use only concurrent statements14 ECE 448 – FPGA and ASIC Design with VHDL• concurrent signal assignment ()Simple rules for beginnersFor circuits composed of - simple logic operations (logic gates) - simple arithmetic operations (addition, subtraction, multiplication) - shifts/rotations by a constantuse15 ECE 448 – FPGA and ASIC Design with VHDLSimple rules for beginnersFor circuits composed of - multiplexers - decoders, encoders - tri-state buffersuse• conditional concurrent signal assignment (when-else)• selected concurrent signal assignment (with-select-when)16 ECE 448 – FPGA and ASIC Design with VHDLLeft vs. right side of the assignment <=<= when-elsewith-select <= Left sideRight side•Internal signals (defined in a given architecture)•Ports of the mode - out - inout - bufferExpressions including:•Internal signals (defined in a given architecture)•Ports of the mode - in - inout - buffer17 ECE 448 – FPGA and ASIC Design with VHDLArithmetic operationsSynthesizable arithmetic operations:•Addition, +•Subtraction, -•Comparisons, >, >=, <, <=•Multiplication, *•Division by a power of 2, /2**6(equivalent to right shift)•Shifts by a constant, SHL, SHR18 ECE 448 – FPGA and ASIC Design with VHDLArithmetic operationsThe result of synthesis of an arithmeticoperation is a - combinational circuit - without pipelining.The exact internal architecture used (and thus delay and area of the circuit)may depend on the timing constraints specifiedduring synthesis (e.g., the requested maximumclock frequency).19 ECE 448 – FPGA and ASIC Design with VHDLOperations on Unsigned NumbersFor operations on unsigned numbersUSE ieee.std_logic_unsigned.alland signals (inputs/outputs) of the typeSTD_LOGIC_VECTORORUSE ieee.std_logic_arith.alland signals (inputs/outputs) of the typeUNSIGNED20 ECE 448 – FPGA and ASIC Design with VHDLOperations on Signed NumbersFor operations on signed numbersUSE ieee.std_logic_signed.alland signals (inputs/outputs) of the typeSTD_LOGIC_VECTORORUSE ieee.std_logic_arith.alland signals (inputs/outputs) of the typeSIGNED21 ECE 448 – FPGA and ASIC Design with VHDLSigned and Unsigned TypesBehave exactly like STD_LOGIC_VECTORplus, they determine whether a given vectorshould be treated as a signed or unsigned number.Require USE ieee.std_logic_arith.all;22 ECE 448 – FPGA and ASIC Design with VHDLInteger TypesOperations on signals (variables)of the integer types: INTEGER, NATURAL,and their sybtypes, such as TYPE day_of_month IS RANGE 0
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