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MASON ECE 448 - Lecture 6 FPGA devices

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FPGA devicesRequired reading (1)Required Reading (2)World of Integrated CircuitsSlide 5Slide 6Which Way to Go?Other FPGA AdvantagesMajor FPGA VendorsXilinxXilinx FPGA FamiliesSlide 12Slide 13CLB StructureSlide 15CLB Slice StructureLUT (Look-Up Table) Functionality5-Input Functions implemented using two LUTsSlide 19Distributed RAMShift RegisterShift RegisterCarry & Control LogicFast Carry LogicAccessing Carry LogicBlock RAM (BRAM)Block RAMSpartan-3 Block RAM AmountsSlide 29Block RAM Port Aspect RatiosSlide 31Single-Port Block RAMDual-Port Block RAMDual-Port Bus FlexibilityTwo Independent Single-Port RAMsBlock RAM Waveforms – WRITE_FIRSTBlock RAM Waveforms – READ_FIRSTBlock RAM Waveforms – NO_CHANGEEmbedded Multipliers18 x 18 Embedded Multiplier18 x 18 MultiplierSlide 42Asynchronous 18-bit Multiplier18-bit Multiplier with RegisterInput/Output Blocks (IOBs)Basic I/O Block StructureIOB FunctionalityRouting ResourcesSlide 49Long and Hex LinesDouble and Direct LinesSpartan-3 Family AttributesSpartan-3 FPGA Family MembersSlide 54Device Part MarkingGeorge Mason University ECE 448 – FPGA and ASIC Design with VHDLFPGA devicesECE 448Lecture 62 ECE 448 – FPGA and ASIC Design with VHDLRequired reading (1)• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 3.6.5 Field-Programmable Gate Arrays3 ECE 448 – FPGA and ASIC Design with VHDLRequired Reading (2)• Xilinx, Inc. Spartan-3 FPGA Introduction• Features• Architectural Overview• Package Marking Spartan-3 FPGA Functional Description • CLB Overview, • Block RAM Overview• Dedicated Multipliers• Interconnect4 ECE 448 – FPGA and ASIC Design with VHDLWorld of Integrated CircuitsIntegrated CircuitsFull-CustomASICsSemi-CustomASICsUser ProgrammableSPLD FPGAPAL PLA PMLLUT(Look-Up Table)MUX GatesCPLD5 ECE 448 – FPGA and ASIC Design with VHDL• designs must be sent for expensive and time consuming fabrication in semiconductor foundry• bought off the shelf and reconfigured by designers themselvesTwo competing implementation approachesASICApplication SpecificIntegrated CircuitFPGAField ProgrammableGate Array• designed all the way from behavioral description to physical layout• no physical layout design; design ends with a bitstream used to configure a device6 ECE 448 – FPGA and ASIC Design with VHDLBlock RAMsBlock RAMsConfigurableLogicBlocksI/OBlocksWhat is an FPGA?BlockRAMs7 ECE 448 – FPGA and ASIC Design with VHDLWhich Way to Go?Off-the-shelfLow development costShort time to marketReconfigurabilityHigh performanceASICs FPGAsLow powerLow cost inhigh volumes8 ECE 448 – FPGA and ASIC Design with VHDLOther FPGA Advantages•Manufacturing cycle for ASIC is very costly, lengthy and engages lots of manpower•Mistakes not detected at design time have large impact on development time and cost•FPGAs are perfect for rapid prototyping of digital circuits•Easy upgrades like in case of software•Unique applications•reconfigurable computing9 ECE 448 – FPGA and ASIC Design with VHDLMajor FPGA VendorsSRAM-based FPGAs•Xilinx, Inc.•Altera Corp.•Atmel•Lattice SemiconductorFlash & antifuse FPGAs•Actel Corp.•Quick Logic Corp.Share over 60% of the market10 ECE 448 – FPGA and ASIC Design with VHDLXilinxPrimary products: FPGAs and the associated CAD softwareMain headquarters in San Jose, CAFabless* Semiconductor and Software CompanyUMC (Taiwan) {*Xilinx acquired an equity stake in UMC in 1996}Seiko Epson (Japan)TSMC (Taiwan)Programmable Logic DevicesISE Alliance and Foundation Series Design Software11 ECE 448 – FPGA and ASIC Design with VHDLXilinx FPGA Families•Old families•XC3000, XC4000, XC5200•Old 0.5µm, 0.35µm and 0.25µm technology. Not recommended for modern designs.•High-performance families•Virtex (0.22µm)•Virtex-E, Virtex-EM (0.18µm)•Virtex-II, Virtex-II PRO (0.13µm)•Virtex-4 (0.09µm)•Low Cost Family•Spartan/XL – derived from XC4000•Spartan-II – derived from Virtex•Spartan-IIE – derived from Virtex-E•Spartan-312 ECE 448 – FPGA and ASIC Design with VHDL13 ECE 448 – FPGA and ASIC Design with VHDLSpartan-3 Family General ArchitectureGeorge Mason University ECE 448 – FPGA and ASIC Design with VHDLCLB Structure15 ECE 448 – FPGA and ASIC Design with VHDLCLB Structure16 ECE 448 – FPGA and ASIC Design with VHDLCLB Slice Structure•Each slice contains two sets of the following:•Four-input LUT•Any 4-input logic function,•or 16-bit x 1 sync RAM (SLICEM only)•or 16-bit shift register (SLICEM only)•Carry & Control•Fast arithmetic logic•Multiplier logic•Multiplexer logic•Storage element•Latch or flip-flop•Set and reset•True or inverted inputs•Sync. or async. control17 ECE 448 – FPGA and ASIC Design with VHDLLUT (Look-Up Table) Functionality•Look-Up tables are primary elements for logic implementation•Each LUT can implement any function of 4 inputsx1x2x3x4yx1x2yLUTx1x2x3x4y0x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y01000101010011000x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y1111111111110000x1x2x3x4yx1x2x3x4yx1x2yx1x2yLUTx1x2x3x4y0x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y01000101010011000x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y01000101010011000x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y11111111111100000x10x2x3x40 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1y111111111111000018 ECE 448 – FPGA and ASIC Design with VHDL5-Input Functions implemented using two LUTs•One CLB Slice can implement any function of 5 inputs•Logic function is partitioned between two LUTs•F5 multiplexer selects LUTA4A3A2A1WS DIDLUTROMRAM10F4F3F2F1A4A3A2A1WS DIDLUTROMRAMF5GXORGnBXBX10BXXF5A4A3A2A1WS DIDLUTROMRAMA4A3A2A1WS DIDLUTROMRAM1010F4F3F2F1A4A3A2A1WS DIDLUTROMRAMA4A3A2A1WS DIDLUTROMRAMF5GXORGF5GXORGnBXBX10nBXBX10BXXF519 ECE 448 – FPGA and ASIC Design with VHDL5-Input Functions implemented using two LUTsLUTLUTX5X4X3X2X1Y0 0 0 0 0 00 0 0 0 1 10 0 0 1 0 00 0 0 1 1 00 0 1 0 0 10 0 1 0 1 10 0 1 1 0 00 0 1 1 1 00 1 0 0 0 10 1 0 0 1 00 1 0 1 0 00 1 0 1 1 10 1 1


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