Introduction to Experiment 6 Internal FPGA Memories, Pseudo Random Number Generator, Advanced Testbenches ECE 448 Spring 2009SourcesSlide 3Slide 4Task 1 – Browsing ModeTask 2 – Edit ModeTask 3 – InitializePseudo Random Number Generator (PRNG)Linear Feedback Shift Register (LFSR)Slide 10Task 4 – SortingTask 5 – Advanced TestbenchTask 5 – Format of an input fileTask 6 : Different Memory TypesTask 7: Dual-port MemoryIntroduction to Core Generator (Hands-on Session)Introduction to Experiment 6Internal FPGA Memories,Pseudo Random Number Generator, Advanced TestbenchesECE 448Spring 20092ECE 448 – FPGA and ASIC Design with VHDLSources• Lecture 14 Xilinx FPGA Memories• Lecture 11 Advanced Testbenches• P. Chu, FPGA Prototyping by VHDL Examples Chapter 11, Xilinx Spartan-3 Specific Memory•Sundar Rajan, Essential VHDL: RTL Synthesis Done RightChapter 14, starting from “Design Verification” (handout distributed in class)3ECE 448 – FPGA and ASIC Design with VHDLSources• XAPP463 Using Block RAM in Spartan-3 Generation FPGAs Google search: XAPP463• XAPP464 Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs Google search: XAPP464• XST User Guide, Section: Coding Techniques Google search: XST User Guide (PDF) http://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode.html (HTML)• ISE In-Depth Tutorial, Section: Creating a CORE Generator Module Google search: ISE In-Depth TutorialAddrDinDoutPRNGSORTING/EDITRAMCONTROLINPUTINTERFACEOUTPUTINTERFACECURRENTADDRESjoystickTwo 7-segmentdisplays8 LEDsCurr_AddrCurr_Addrfrom CONTROLfrom CONTROLTask 1 – Browsing Mode00 0102030405….FAFBFCFDFEFF00 0102030405….FAFBFCFDFEFFAddress DataCurrent AddressTwo 7-SegmentDisplays(in hexadecimalnotation)Joystick up = Increment AddressJoystick down = Decrement Address8 LEDs(in binarynotation)Value at Current Address256x8 RAMTask 2 – Edit Mode00 0102030405….FAFBFCFDFEFF00 0102030405=>06….FAFBFCFDFEFFAddress DataCurrent AddressTwo 7-SegmentDisplays(in hexadecimalnotation)Joystick up = Increment AddressJoystick down = Decrement Address8 LEDs(in binarynotation)Value at Current Address256x8 RAMJoystick Enter = EditJoystick up = Increment DataJoystick down = Decrement DataJoystick Enter = ApproveTask 3 – Initialize00 0102030405….FAFBFCFDFEFF25 879426B5C6….7A5B34438978Address DataJoystick Enter = Initialize with Pseudorandom Values256x8 RAMPseudo Random Number Generator (PRNG)•A pseudorandom number generator (PRNG) is an algorithm for generating a sequence of numbers that approximates the properties of random numbers. The sequence is not truly random in that it is completely determined by a relatively small set of initial values. •A PRNG can be started from an arbitrary starting state, using a seed state. It will always produce the same sequence thereafter when initialized with that state. The maximum length of the sequence before it begins to repeat is determined by the size of the state, measured in bits.•PRNG Circuit can be constructed from a Linear Feedback Shift Register (LFSR) circuit*from http://en.wikipedia.org/wiki/PRNGLinear Feedback Shift Register (LFSR)•A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. •The only linear functions of single bits are xor and inverse-xor; thus it is a shift register whose input bit is driven by the exclusive-or (xor) of some bits of the overall shift register value.*from http://en.wikipedia.org/wiki/LFSR8-bit LFSR (Linear Feedback Shift Register)with the period of 28-1 8RR0R1R2R3R4R5R6R7=D flip-flop with set or reset determining its initialvalue after “soft” resetRun for 8 clock cycles before using a new output value.Task 4 – Sorting00 0102030405….FAFBFCFDFEFF25 3744565778….B4B6B8CCD4FFAddress DataJoystick Enter = sorting using one of the following typessorting signed numbers in the descending ordersorting signed numbers in the ascending ordersorting unsigned numbers in the descending ordersorting unsigned numbers in the ascending orderJoystick Up changing sorting type256x8 RAMTask 5 – Advanced TestbenchProcessesGeneratingInputStimuli Design Under Test (DUT)ProcessComparingActual Outputsvs.Expected OutputsDesignCorrect/IncorrectYes/NoTestvector file(s)Task 5 – Format of an input filenumber of entries to be sorted (in decimal)empty linenumbers to be sorted in the initial order (in the hexadecimal notation, one number per line)empty linenumbers after sorting (in the hexadecimal notation, one number per line)6B489A358617858617889A3B4Task 6 : Different Memory TypesMemory Distributed (MLUT-based)Block RAM-based(BRAM-based)InferredMemoryManuallyUsing Core GeneratorTask 7: Dual-port Memory•Replace Single-Port RAM with Dual-Port RAM and redesign Sorting Logic accordingly•Calculate the gain in terms of - average execution time - smaller resource utilization.Introduction to Core Generator(Hands-on
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