Finite State Machines State Diagrams, State Tables, Algorithmic State Machine (ASM) Charts, and VHDL codeRequired readingSlide 3Structure of a Typical Digital SystemDatapath (Execution Unit)Controller (Control Unit)ControllerFinite State MachinesHardware Design with RTL VHDLSlide 10Finite State Machines (FSMs)Moore FSMMealy FSMSlide 14Moore MachineMealy MachineMoore vs. Mealy FSM (1)Moore vs. Mealy FSM (2)Moore FSM - Example 1Mealy FSM - Example 1Moore & Mealy FSMs – Example 1Slide 22FSMs in VHDLSlide 24Slide 25Slide 26Moore FSM in VHDL (1)Moore FSM in VHDL (2)Slide 29Mealy FSM in VHDL (1)Mealy FSM in VHDL (2)Slide 32Algorithmic State MachineElements used in ASM charts (1)State BoxDecision BoxConditional Output BoxASMs representing simple FSMsSlide 39Slide 40Slide 41Slide 42Slide 43Example 2: VHDL code (3)Slide 45ASM Chart for Mealy FSM – Example 3Slide 47Example 3: VHDL code (2)Example 3: VHDL code (3)Slide 50Slide 51Slide 52ASM Chart for Control Unit - Example 4Example 4: VHDL code (1)Example 4: VHDL code (2)Example 4: VHDL code (3)George Mason UniversityECE 448 – FPGA and ASIC Design with VHDLFinite State MachinesState Diagrams,State Tables, Algorithmic State Machine (ASM) Charts, and VHDL codeECE 448Lecture 72ECE 448 – FPGA and ASIC Design with VHDLRequired reading• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 8, Synchronous Sequential Circuits Sections 8.1-8.5Chapter 8.10, Algorithmic State Machine (ASM) Charts• P. Chu, FPGA Prototyping by VHDL Examples Chapter 5, FSM3ECE 448 – FPGA and ASIC Design with VHDLDatapathvs.Controller4ECE 448 – FPGA and ASIC Design with VHDLStructure of a Typical Digital SystemDatapath(Execution Unit)Controller(Control Unit)Data InputsData OutputsControl InputsControl OutputsControl SignalsStatusSignals5ECE 448 – FPGA and ASIC Design with VHDLDatapath (Execution Unit)•Manipulates and processes data•Performs arithmetic and logic operations, shifting, and other data-processing tasks•Is composed of registers, gates, multiplexers, decoders, adders, comparators, ALUs, etc.•Provides all necessary resources and interconnects among them to perform specified task•Interprets control signals from the Controller and generates status signals for the Controller6ECE 448 – FPGA and ASIC Design with VHDLController (Control Unit)•Controls data movements in the Datapath by switching multiplexers and enabling or disabling resourcesExample: enable signals for registersExample: control signals for muxes •Provides signals to activate various processing tasks in the Datapath•Determines the sequence the operations performed by Datapath•Follows Some ‘Program’ or Schedule7ECE 448 – FPGA and ASIC Design with VHDLController•Controller can be programmable or non-programmable•Programmable•Has a program counter which points to next instruction•Instructions are held in a RAM or ROM externally•Microprocessor is an example of programmable controller•Non-Programmable•Once designed, implements the same functionality•Another term is a “hardwired state machine” or “hardwired instructions”•In the following several lectures we will be focusing on non-programmable controllers.8ECE 448 – FPGA and ASIC Design with VHDLFinite State Machines•Digital Systems and especially their Controllers can be described as Finite State Machines (FSMs)•Finite State Machines can be represented using•State Diagrams and State Tables - suitable for simple digital systems with a relatively few inputs and outputs•Algorithmic State Machine (ASM) Charts - suitable for complex digital systems with a large number of inputs and outputs•All these descriptions can be easily translated to the corresponding synthesizable VHDL code9ECE 448 – FPGA and ASIC Design with VHDLHardware Design with RTL VHDLPseudocodeDatapath ControllerBlockdiagramBlockdiagramState diagramor ASM chartVHDL code VHDL code VHDL codeInterface10ECE 448 – FPGA and ASIC Design with VHDLFinite State MachinesRefresher11ECE 448 – FPGA and ASIC Design with VHDLFinite State Machines (FSMs)•Any Circuit with Memory Is a Finite State Machine•Even computers can be viewed as huge FSMs•Design of FSMs Involves•Defining states•Defining transitions between states•Optimization / minimization•Manual Optimization/Minimization Is Practical for Small FSMs Only12ECE 448 – FPGA and ASIC Design with VHDLMoore FSM•Output Is a Function of a Present State OnlyPresent StateregisterNext StatefunctionOutputfunctionInputsPresent StateNext StateOutputsclockreset13ECE 448 – FPGA and ASIC Design with VHDLMealy FSM•Output Is a Function of a Present State and InputsNext StatefunctionOutputfunctionInputsPresent StateNext StateOutputsPresent Stateregisterclockreset14ECE 448 – FPGA and ASIC Design with VHDLState Diagrams15ECE 448 – FPGA and ASIC Design with VHDLMoore Machinestate 1 /output 1state 2 /output 2transitioncondition 1transitioncondition 216ECE 448 – FPGA and ASIC Design with VHDLMealy Machinestate 1state 2transition condition 1 /output 1transition condition 2 /output 217ECE 448 – FPGA and ASIC Design with VHDLMoore vs. Mealy FSM (1)•Moore and Mealy FSMs Can Be Functionally Equivalent•Equivalent Mealy FSM can be derived from Moore FSM and vice versa•Mealy FSM Has Richer Description and Usually Requires Smaller Number of States•Smaller circuit area18ECE 448 – FPGA and ASIC Design with VHDLMoore vs. Mealy FSM (2)•Mealy FSM Computes Outputs as soon as Inputs Change•Mealy FSM responds one clock cycle sooner than equivalent Moore FSM•Moore FSM Has No Combinational Path Between Inputs and Outputs•Moore FSM is more likely to have a shorter critical path19ECE 448 – FPGA and ASIC Design with VHDLMoore FSM - Example 1•Moore FSM that Recognizes Sequence “10”S0 / 0 S1 / 0 S2 / 1000111resetMeaning of states:S0: No elements of the sequenceobservedS1: “1”observedS2: “10”observed20ECE 448 – FPGA and ASIC Design with VHDLMealy FSM - Example 1•Mealy FSM that Recognizes Sequence “10”S0 S10 / 01 / 0 1 / 00 / 1resetMeaning of states:S0: No elements of the sequenceobservedS1: “1”observed21ECE 448 – FPGA and ASIC Design with VHDLMoore & Mealy FSMs – Example 1clockinputMooreMealy0 1 0 0 0S0 S1 S2 S0 S0S0 S1 S0 S0 S022ECE 448 – FPGA and ASIC Design with VHDLFinite State Machinesin
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