Slide 1Required readingSlide 3An algorithm for multiplicationExpected behavior of the multiplierDatapath for the multiplierASM chart for the multiplierASM chart for the multiplier control circuitVHDL code of multiplier circuit (1)VHDL code of multiplier circuit (2)VHDL code of multiplier circuit (3)Slide 12VHDL code of multiplier circuit (4)Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23LatencyThroughputPipelining—ConceptualSlide 27George Mason University ECE 448 – FPGA and ASIC Design with VHDLECE 448Lecture 14Multipliers2 ECE 448 – FPGA and ASIC Design with VHDLRequired reading• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 10.2.3, Shift-and-Add MultiplierChapter 10.2.5, Arithmetic MeanChapter 10.2.6, Sort Operation3 ECE 448 – FPGA and ASIC Design with VHDLShift-and-Add Multiplier4 ECE 448 – FPGA and ASIC Design with VHDLAn algorithm for multiplication(a) Manual methodMultiplicand, A11ProductMultiplier, B1001111 1 0 110110000101101 001111Binary13111313143DecimalP = 0 ; for i = 0 ton 1 doifb i = 1 thenP = P + A ; end if; Left-shiftA ; end for;(b) Pseudo-code –5 ECE 448 – FPGA and ASIC Design with VHDLExpected behavior of the multiplier6 ECE 448 – FPGA and ASIC Design with VHDLDatapath for the multiplierE L E L E 0 DataA LAEAA Clock P DataP RegisterEPSum 0 z B b 0 DataB LBEB+ 2nn n Shift-leftregisterShift-right registern n 2n 2nPsel1 0 2n2n7 ECE 448 – FPGA and ASIC Design with VHDLASM chart for the multiplierShift left A , Shift right B DoneP P A + B 0 = ? P 0 s Load Ab 0 Reset S30 1 0 1 0 1 s S1S21 0 Load B8 ECE 448 – FPGA and ASIC Design with VHDLASM chart for the multiplier control circuitEPz b 0 Reset S30 1 0 1 s 0 1 DonePsel 0 = EP, s 0 1 S1S2Psel 1 = EA EB, ,9 ECE 448 – FPGA and ASIC Design with VHDLVHDL code of multiplier circuit (1)LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;USE work.components.all ;ENTITY multiply ISGENERIC ( N : INTEGER := 8; NN : INTEGER := 16 ) ;PORT ( Clock : IN STD_LOGIC ; Resetn : IN STD_LOGIC ; LA, LB, s : IN STD_LOGIC ; DataA : IN STD_LOGIC_VECTOR(N–1 DOWNTO 0) ; DataB : IN STD_LOGIC_VECTOR(N–1 DOWNTO 0) ; P : BUFFER STD_LOGIC_VECTOR(N–1 DOWNTO 0) ; Done : OUT STD_LOGIC ) ;END multiply ;10 ECE 448 – FPGA and ASIC Design with VHDLVHDL code of multiplier circuit (2)ARCHITECTURE Behavior OF multiply ISTYPE State_type IS ( S1, S2, S3 ) ;SIGNAL y : State_type ;SIGNAL Psel, z, EA, EB, EP, Zero : STD_LOGIC ;SIGNAL B, N_Zeros : STD_LOGIC_VECTOR(N–1 DOWNTO 0) ;SIGNAL A, Ain, DataP, Sum : STD_LOGIC_VECTOR(NN–1 DOWNTO 0) ;BEGINFSM_transitions: PROCESS ( Resetn, Clock )BEGINIF Resetn = '0’ THENy <= S1 ;ELSIF (Clock'EVENT AND Clock = '1') THENCASE y ISWHEN S1 =>IF s = '0' THEN y <= S1 ; ELSE y <= S2 ; END IF ;WHEN S2 =>IF z = '0' THEN y <= S2 ; ELSE y <= S3 ; END IF ;WHEN S3 =>IF s = '1' THEN y <= S3 ; ELSE y <= S1 ; END IF ;END CASE ;END IF ;END PROCESS ;11 ECE 448 – FPGA and ASIC Design with VHDLVHDL code of multiplier circuit (3)FSM_outputs: PROCESS ( y, s, B(0) )BEGINEP <= '0' ; EA <= '0' ; EB <= '0' ; Done <= '0' ; Psel <= '0';CASE y ISWHEN S1 =>EP <= '1‘ ;WHEN S2 =>EA <= '1' ; EB <= '1' ; Psel <= '1‘ ;IF B(0) = '1' THEN EP <= '1' ; ELSE EP <= '0' ; END IF ;WHEN S3 =>Done <= '1‘ ;END CASE ;END PROCESS ;12 ECE 448 – FPGA and ASIC Design with VHDLDatapath for the multiplierE L E L E 0 DataA LAEAA Clock P DataP RegisterEPSum 0 z B b 0 DataB LBEB+ 2nn n Shift-leftregisterShift-right registern n 2n 2nPsel1 0 2n2n13 ECE 448 – FPGA and ASIC Design with VHDLVHDL code of multiplier circuit (4)- - Define the datapath circuitZero <= '0' ;N_Zeros <= (OTHERS => '0' ) ;Ain <= N_Zeros & DataA ;ShiftA: shiftlne GENERIC MAP ( N => NN )PORT MAP ( Ain, LA, EA, Zero, Clock, A ) ;ShiftB: shiftrne GENERIC MAP ( N => N )PORT MAP ( DataB, LB, EB, Zero, Clock, B ) ;z <= '1' WHEN B = N_Zeros ELSE '0' ;Sum <= A + P ;- - Define the 2n 2-to-1 multiplexers for DataPGenMUX: FOR i IN 0 TO NN–1 GENERATEMuxi: mux2to1 PORT MAP ( Zero, Sum(i), Psel, DataP(i) ) ;END GENERATE;RegP: regne GENERIC MAP ( N => NN )PORT MAP ( DataP, Resetn, EP, Clock, P ) ;END Behavior ;14 ECE 448 – FPGA and ASIC Design with VHDLArray Multiplier15 ECE 448 – FPGA and ASIC Design with VHDLNotationa Multiplicand ak-1ak-2 . . . a1 a0x Multiplier xk-1xk-2 . . . x1 x0p Product (a x) p2k-1p2k-2 . . . p2 p1 p016 ECE 448 – FPGA and ASIC Design with VHDLUnsigned Multiplicationa4 a3 a2 a1 a0x4 x3 x2 x1 x0xa4x0 a3x0 a2x0 a1x0 a0x0a4x1 a3x1 a2x1 a1x1 a0x1a4x2 a3x2 a2x2 a1x2 a0x2a4x3 a3x3 a2x3 a1x3 a0x3a4x4 a3x4 a2x4 a1x4 a0x4p0p1p9p2p3p4p5p6p7p8+ax0 20ax1 21ax2 22ax3 23ax4 2417 ECE 448 – FPGA and ASIC Design with VHDL5 x 5 Array Multiplier18 ECE 448 – FPGA and ASIC Design with VHDLArray Multiplier - Basic CellxycincoutsFA19 ECE 448 – FPGA and ASIC Design with VHDLArray Multiplier – Modified Basic Cellsi-1cici+1siFAxnam20 ECE 448 – FPGA and ASIC Design with VHDL5 x 5 Array Multiplier with modified cells21 ECE 448 – FPGA and ASIC Design with VHDLPipelined 5 x 5 Multiplier22 ECE 448 – FPGA and ASIC Design with VHDLArray Multiplier – Modified Basic Cellsi-1cici+1siFAxnamFlip-flops23 ECE 448 – FPGA and ASIC Design with VHDLTiming parametersdefinitionunitsdelayclock period Tclock frequencytime from pointpointrising edge rising edgeof clock1clock periodnsnsMHzlatencythroughputtime from inputoutput#output bits/time unitnsMbits/s24 ECE 448 – FPGA and ASIC Design with VHDLLatencyD QclkD QclkCombinationalLogicCombinationalLogicCombinationalLogicCombinationalLogicD Qclktop-level entity•Latency is the time between input(n) and output(n)•i.e. time it takes from first input to first output, second input to second output, etc.•Latency is usually constant for a system (but not always)•Also called input-to-output latency•Count the number of rising edges of the clock!•In this example, 3 rising edges from input to output latency is 3 cycles•Latency is measured in clock cycles (then translated to seconds)•In this example, say clock period is 10 ns, then latency is 30 ns input outputclkinputinput(0)input(1) input(2)output(unknown) output(0) output(1)8 bits8 bits100 MHz25 ECE 448 – FPGA and ASIC Design with VHDLThroughputD QclkD QclkCombinationalLogicCombinationalLogicCombinationalLogicCombinationalLogicD Qclktop-level
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