Slide 1Structure of a Typical Digital SystemHardware Design with RTL VHDLSteps of the Design ProcessSteps of the Design Process Practiced in ClassSlide 6Slide 7Simulation results for the sort operation (1) Loading the registers and starting sortingSimulation results for the sort operation (2) Completing sorting and reading out registersSorting - ExamplePseudocodeSlide 12Lecture 13RTL Design MethodologySortingStructure of a Typical Digital SystemDatapath(Execution Unit)Controller(Control Unit)Data InputsData OutputsControl InputsControl OutputsControl SignalsStatusSignalsHardware Design with RTL VHDLPseudocodeDatapath ControllerBlockdiagramBlockdiagramState diagramor ASM chartVHDL code VHDL code VHDL codeInterfaceSteps of the Design Process1. Text description2. Interface3. Pseudocode4. Block diagram of the Datapath5. Interface with the division into the Datapath and the Controller6. ASM chart of the Controller7. RTL VHDL code8. Testbench9. Debugging10. Synthesis and implementation11. Experimental testingSteps of the Design ProcessPracticed in Class1. Text description2. Interface3. Pseudocode4. Block diagram of the Datapath5. Interface with the division into the Datapathand the Controller6. ASM chart of the Controller7. RTL VHDL code8. Testbench9. Debugging10. Synthesis and implementation11. Experimental testingSortingExampleSorting - Required InterfaceSortClockResetnDataInNDataOutNDoneRAddLWrInitS(0=initialization 1=computations)RdSimulation results for the sort operation (1)Loading the registers and starting sortingSimulation results for the sort operation (2)Completing sorting and reading out registersSorting - ExampleBeforesortingDuring SortingAftersortingaddress01233 3 2 2 1 1 1 12 2 3 3 3 3 2 24 4 4 4 4 4 4 31 1 1 1 2 2 3 4i=0 i=0 i=0 i=1 i=1 i=2j=1 j=2 j=3 j=2 j=3 j=3Legend:position of memory indexed by iposition of memory indexed by jijPseudocodewait for s=1for i=0 to k-2 doA = M[i]for j=i+1 to k-1 doB = M[j]if A > B thenM[i] = BM[j] = AA = M[i]end ifend forend forDonewait for s=0go to the beginningDINDOUTADDRWECLKENCLKRSTENCLKRSTA>B10WrInitWrInitClockClockClockResetnResetnWr10BoutAinBinAgtBAddrInt0101DataIn RAddRdDataOutCselENCLKLDRSTResetnENCLKLDRSTResetnLIEIClockLJEJClock= k-2= k-1zizjNLLLLNNNNNABMuxABijABDataDinWe0L+1Block diagram of the
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