Slide 1AgendaSlide 3IntroductionSlide 5Slide 6Slide 7Design Flow - OverviewWhat does Astro™ do?Where does the Gate Level Netlist come from? 1st Input to Astro™Standard Cell Library 2nd Input to Astro™Basic Devices and InterconnectTransistor or Device RepresentationWhat is “Physical Layout”?Process of Device FabricationWafer Representation of Layout PolygonsContacts: Connecting Metal 1 to Poly/Diff’nWhat is meant by “0.xx um Technology”?Comparing TechnologiesRelative Device Drive StrengthsGate Drive Strength ExampleDrive/Buffering Rules: Max Transition/CapTiming Constraints 3rd Input to Astro™Concept of Place and RouteConcepts of PlacementConcepts of RoutingSlide 27Design Flow – FloorplanDesign Must Be Floorplanned Before P&RI/O Placement and Chip Package RequirementsGuidelines for a Good FloorplanDefining the Power/Ground Grid and BlockagesSlide 33Design Flow – Timing Driven PlacementTiming ConstraintsCell and Net DelaysTiming Driven PlacementLogic OptimizationsSlide 39Design Flow – Clock Tree SynthesisClock Tree TopologiesAfter Clock Tree SynthesisGated - CTSEffects of CTSSlide 45Design Flow – RoutingTiming Driven RoutingConcept of Routing TracksGrid-Based Routing SystemSlide 50What Happens After Place and Route?Formal VerificationTiming VerificationPhysical VerificationFabricationMask Generation – GDSII / StreamExample Design – Cory Ellinger Independent StudyBlock DiagramBlock Diagram – Critical PathMajor Physical Design StepsFloorplanningSlide 62FloorplanFloorplan Showing Logic ModulesPlacementAutoPlace of Logic ModulesDesign PlacementReset NetPre-Clock Tree SynthesisClock Tree SynthesisPost Clock Tree SynthesisRouted DesignRoute (zoom)Slide 74ASIC Back-End DesignLecture given by Saadat Khan, BAE SystemsSlides prepared by Jamie Bernard, BAE SystemsAgenda•Introduction•Design Flow–Overview–Floorplan–Timing Driven Placement–Clock Tree Synthesis–Routing•Verification•Design ExampleIntroductionIntroductionIntroduction•Technological Advances–19th Century - Steel–20th Century – Silicon•Growth in Microelectronic (Silicon) Technology–Moore’s Law (# of transistors double/18 months)–One Transistor–Small Scale Integration (SSI)•Multiple Devices (Transistor / Resistor / Diodes)•Possibility to create more than one logic gate (Inverter, etc)–Large Scale Integration (LSI)•Systems with at least 1000 logic gates (Several thousand transistors)–Very Large Scale Integration•Millions to hundreds of millions of transistors (Microprocessors)–Intel indicates that dual core processors will soon exist that contain 1 billion transistorsIntroduction•Manual (Human) design can occur with small number of transistors•As number of transistors increase through SSI and VLSI, the amount of evaluation and decision making would become overwhelming (Trade-offs)–Maintaining performance requirements (Power / Speed / Area)–Design and implementation times become impractical•How does one create a complex electronic design consisting of millions of transistors? Automate the Process using Computer-Aided Design (CAD) Tools Automate the Process using Computer-Aided Design (CAD) ToolsIntroduction•CAD tools provide several advantages–Ability to evaluate complex conditions in which solving one problem creates other problems–Use analytical methods to assess the cost of a decision–Use synthesis methods to help provide a solution –Allows the process of proposing and analyzing solutions to occur at the same time•Electronic Design Automation–Using CAD tools to create complex electronic designs (ECAD)–Several companies who specialize in EDA•Cadence® Design Systems•Magma® Design Automation Inc.•Synopsys®CAD Tools Allow Large Problems to be SolvedCAD Tools Allow Large Problems to be SolvedDesign FlowDesign FlowDesign Flow - Overview•Generic VLSI Design Flow from System Specification to Fabrication and Testing•Steps prior to Circuit/Physical design are part of the FRONT-END flow•Physical Level Design is part of the BACK-END flow–Physical Design is also known as “Place and Route”•CAD tools are involved in all stages of VLSI design flow–Different tools can be used at different stages due to EDA common data formats*•Synopsys® CAD tool for Physical Design is called Astro™What does Astro™ do?Where does the Gate Level Netlist come from?1st Input to Astro™Standard Cell Library2nd Input to Astro™ •Pre-designed collection of logic functions–OR, AND, XOR, etc•Contains both Layout and Abstract views–Layout (CEL) contains drawn mask layers required for fabrication–Abstract (FRAM) contains only minimal data needed for Astro™–Timing information•Cell Delay / Pin Capacitance•Common height for placement purposes•Integrated circuits are built out of active and passive components, also called devices:–Active devices•Transistors•Diodes–Passive devices•Resistors•Capacitors•Devices are connected together with polysilicon or metal interconnect:–Interconnect can add unwanted or parasitic capacitance, resistance and inductance effects•Device types and sizes are process or technology specific:–The focus here is on CMOS technologyBasic Devices and Interconnect38Transistor or Device RepresentationGates are made up of active devices or transistors.Gates are made up of active devices or transistors.CMOS Inverter ExampleOUTINGate SchematicINOUTPMOSNMOSTransistor or Device ViewVDDGND37What is “Physical Layout”?Physical Layout – Topography of devices and interconnects, made up of polygons that represent different layers of material. CMOS Inverter ExampleNMOSPMOSOUTVDDGNDPhysical or Layout ViewININOUTPMOSNMOSTransistor or Device ViewVDDGND39Layout or Mask (aerial) viewSilicon SubstrateProcess of Device Fabrication•Devices are fabricated vertically on a silicon substrate wafer by layering different materials in specific locations and shapes on top of each other•Each of many process masks defines the shapes and locations of a specific layer of material (diffusion, polysilicon, metal, contact, etc)•Mask shapes, derived from the layout view, are transformed to silicon via photolithographic and chemical processesWafer (cross-sectional) view40Wafer Representation of Layout PolygonsExample of complimentary devices in 0.25 um CMOS technology or process. InputVDDGNDOutputPMOSNMOS0.25 umAerial or Layout ViewWafer Cross-sectional View41Contacts: Connecting Metal 1 to
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