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MASON ECE 448 - Lab 1 Introduction to Aldec Active HDL

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Slide 1Slide 2MLU Block DiagramSlide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Block diagramArithmetic Functions in VHDL (1)Arithmetic Functions in VHDL (2)ECE 448 – FPGA and ASIC Design with VHDL George Mason UniversityLab 1Introduction to Aldec Active HDL Implementing Combinational Logic in VHDLExample: MLUPart 1Introduction to Aldec Active-HDLMLU Block DiagramBANEG_ANEG_BIN0IN1IN2IN3 OUTPUTSEL1SEL0MUX_4_1L0L1NEG_YYY1A1B1MUX_0MUX_1MUX_2MUX_3Experiment 1Problem 1ALU of Motorola 68HC11X-index registerY-index registerStack PointerProgram CounterCondition Code RegisterRegister structure of MC6811Double Accumulator DAccumulators A and B orIX015IY015SP015PC015CCR07D0157 70 0A BS X H I N Z V CCondition Code RegisterCCR07S X H I N Z V Ccarry / borrowoverflowzeronegativeI-interrupt maskhalf-carry (from bit 3)X-interrupt maskstop disableDefinition of the Condition Code Register flags (1)Z = 1 if result = 0 0 otherwiseZero flag - ZN = sign bit of the result R7 - for an 8-bit resultNegative flag- Nzero resultnegative resultDefinition of the Condition Code Register flags (2)C = 1 if result > MAX_UNSIGNED or result < 0 0 otherwisewhere MAX_UNSIGNED = 28-1 for 8-bit resultsV = 1 if result > MAX_SIGNED or result < MIN_SIGNED 0 otherwisewhere MAX_SIGNED = 27-1 andMIN_SIGNED = -27 for 8-bit resultsCarry flag - COverflow flag - Vout-of-range for unsigned numbersout-of-range for signed numbersOverflow for signed numbers (1)Indication of overflow Positive+ Positive= Negative Negative+ Negative= PositiveAddressing modes of the ADDA instructionImmediate modeADDA #$5CDirect modeADDA $1BExtended modeADDA $6D00Indexed modeADDA $56, XADDA $56, YA + $5C  AA+ ($001B)  AA + ($6D00)  AA+(IX+$56)  A A+(IY+$56)  AMAssembly language vs. machine codeAssembly languagemnemonic [operands] ADDA #$4AADDA $5B78 Machine code$8B $4Aopcode [operands]$BB $5B $78NEGB$50Logic instructions1. AND Acc & M  AccAND [A, B]2. OR Acc | M  AccORA [A, B]3. XOR Acc  M  AccEOR [A, B]4. complement X  XCOM [A, B]COMIMM, DIR, EXT, INDN Z V CIMM, DIR, EXT, INDIMM, DIR, EXT, IND0 –0 –0 – INHEXT, IND0 1Arithmetic instructions (1)1. addition Acc + M  Acc Acc + M + C  AccADD [A, B]ADC [A, B]2. subtraction Acc – M  Acc Acc – M – C  AccSUB [A, B]SBC [A, B]IMM, DIR, EXT, INDN Z V CIMM, DIR, EXT, INDEXT, INDINH3. negation -XNEG [A, B]NEGArithmetic instructions (2)N Z V C4. unsigned multiplication A x B  DMULINH– – –Alter data instructions1. 0  registerCLR [A, B]2. 0  memoryCLREXT, INDINHN Z V C0 1 0 00 1 0 03. increment X++INC [A, B]INC4. decrement X--DEC [A, B]DEC– INHEXT, IND INHEXT, IND–Edit instructions - Shifts1. logical shift rightLSR [A, B]LSR2. arithmetic shift rightASR [A, B]ASR3. arithmetic/logical shift leftASL [A, B], LSL [A, B]ASL, LSL INHEXT, IND INHEXT, IND INHEXT, IND007C. . .07C. . .007C. . .N Z V C0Edit instructions - Rotations1. rotation rightROR [A, B]ROR2. rotation leftROL [A, B]ROL INHEXT, IND INHEXT, IND07C. . .007C. . .N Z V CPart 2Mini ALUMnemonic Operation OpcodeADDAB R= A + B 0000ADDAM R = A + M 0001SUBAB R = A - B 0010SUBAM R = A - M 0011NOTA R = NOT A 0100NOTB R = NOT B 0101NOTM R = NOT M 0110ANDAB R = A AND B 0111ANDAM R = A AND M 1000ORAB R = A OR B 1001ORAM R = A OR M 1010XORAB R = A XOR B 1011XORAM R = A XOR M 1100opcodeABMRMini ALU44444Block diagramArithmetic Functions in VHDL (1)To use arithmetic operations involving std_logic_vectors you need to include thefollowing library packages:library ieee;use ieee.std_logic_1164.all;use ieee.STD_LOGIC_UNSIGNED.ALL;Arithmetic Functions in VHDL (2)You can use standard +, - operatorsto perform addition and subtraction: signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0); …… C<= A +


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