ASIC Design FlowSourcesIntroductionIntroductionIntroductionTop Level Digital Design FlowRTL DesignSynthesis + Macro DevelopmentPlace + RoutePhysical VerificationDesign Flow - OverviewWhat does Astro™ do?Where does the Gate Level Netlist come from?1st Input to Astro™Standard Cell Library2nd Input to Astro™Timing Constraints3rd Input to Astro™Concept of Place and RouteConcepts of PlacementConcepts of RoutingDesign Flow – Design SetupDesign Setup Step #1 Creating a Design LibraryTechnology FileDesign Setup Step #2 Attach Reference LibrariesDesign Setup Step #3 Read NetlistDesign Setup Step #4 Expand NetlistDesign Setup Step #5 Create Starting CellDesign Setup Step #6 Bind Netlist to CellDesign Setup Step #7 Preserve the HierarchyDesign Flow – FloorplanDesign Must Be Floorplanned Before P&RI/O Placement and Chip Package RequirementsGuidelines for a Good FloorplanDefining the Power/Ground Grid and BlockagesDesign Flow – Timing Driven PlacementTiming ConstraintsCell and Net DelaysTiming Sanity CheckTiming Driven PlacementLogic OptimizationsDesign Flow – Clock Tree SynthesisClock Tree TopologiesAfter Clock Tree SynthesisGated - CTSEffects of CTSDesign Flow – RoutingTiming Driven RoutingConcept of Routing TracksGrid-Based Routing SystemRouting OperationsGlobal RoutingTrack AssignmentDetailed RoutingSearch and RepairWhat Happens After Place and Route?Formal VerificationTiming VerificationPhysical VerificationFabricationFutureConclusionASIC Design FlowECE 448Lecture 19Sources• Jamie Bernard, Physical Level Design using Synopsys,Scholarly Paper, GMU, 2005• Cory Ellinger,VLSI Design Automation,Independent Research Project,GMU, 2005.IntroductionIntroductionIntroduction• Technological Advances–19thCentury - Steel–20thCentury – Silicon• Growth in Microelectronic (Silicon) Technology– Moore’s Law (# of transistors double/18 months)– One Transistor– Small Scale Integration (SSI)• Multiple Devices (Transistor / Resistor / Diodes)• Possibility to create more than one logic gate (Inverter, etc)– Large Scale Integration (LSI)• Systems with at least 1000 logic gates (Several thousand transistors)– Very Large Scale Integration• Millions to hundreds of millions of transistors (Microprocessors)– Intel indicates that dual core processors will soon exist that contain 1 billion transistorsIntroduction• Manual (Human) design can occur with small number of transistors• As number of transistors increase through SSI and VLSI, the amount of evaluation and decision making would become overwhelming (Trade-offs)– Maintaining performance requirements (Power / Speed / Area)– Design and implementation times become impractical• How does one create a complex electronic consisting of millions of transistors?Automate the Process using Computer-Aided Design (CAD) ToolsAutomate the Process using Computer-Aided Design (CAD) ToolsIntroduction• CAD tools provide several advantages– Ability to evaluate complex conditions in which solving one problem creates other problems– Use analytical methods to assess the cost of a decision– Use synthesis methods to help provide a solution – Allows the process of proposing and analyzing solutions to occurat the same time• Electronic Design Automation– Using CAD tools to create complex electronic designs (ECAD)– Several companies who specialize in EDA• Cadence® Design Systems• Magma® Design Automation Inc.• Synopsys®CAD Tools Allow Large Problems to be SolvedCAD Tools Allow Large Problems to be SolvedDesign FlowDesign FlowTop Level Digital Design FlowRTL DesignPlace + RoutePhysical VerificationSynthesisDesign InceptionDesign CompleteMacro DevelopmentRTL DesignDesign FunctionDigital ToolRTL DesignTestbench DevelopementMixed Mode SimulationFPGA Verification(users disgression)Lint Checking(users digression)Code Coverage(users disgression)Formal VerificationCadence NC VerilogMentor Graphis ModelSimCadence NC VerilogMentor Graphics ModelSimCadence AMS DesignerXilinx ISECadence HalCadence ICTAgilent ADSMatlabDesign Inception Design InceptionSynthesisSynthesis + Macro DevelopmentSystem Interface SimulationCadence ConformalSynthesis + Macro DevelopmentSynthesis + Macro DevelopmentDesign FunctionDigital ToolSynthesisStatic Timing AnalysisLogical EquivalencyDFTPlace + RouteGate-Level SimulationRTLSynopsys DC Cadence RCSynopsys PrimeTimeCadence ConformalSynopsys DFT CompilerCadence RCPlace + RouteCadence NC VerilogMentor Graphics ModelsimRTLMacro GenerationMacro VerificationMacro Rules Generation / Library GenerationMentor Graphics CalibreArtisan/Cadence DFIIArtisanVerification VerificationPlace + RouteFloorplanMacro Placement / Std Cell PlacementPlacement-Based OptimizationClock Tree SynthesisRouteRC ExtractionSignal IntegrityDesign FunctionDigital ToolStatic Timing AnalysisCadence NanoRouteCadence Fire&Ice QXCadence CeltIC / Voltage StormSynopsysPrime-TimeVerificationVerificationCadence EncounterSynthesisSynthesisATPGMentor Graphics FastScanCadence EncounterMetal FillSpare Cells / Decoupling Cap Filler CellsCadence EncounterPhysical VerificationDesign FunctionDigital ToolGDSII Preparation / Schematic PreparationDRCLVSERCSimulation PreparationBack Annotated SimulationLayout / Chip FinishingCadence DFII Cadence DFIICadence NC VerilogCadence VirtuosoPlaced + Routed DesignPlaced + Routed DesignDesign CompleteDesign CompleteMentor Graphics CalibreTop-Level SimulationSynopsys NanosimCadence AMS DesignerDesign Flow - Overview• Generic VLSI Design Flow from System Specification to Fabrication and Testing• Steps prior to Circuit/Physical design are part of the FRONT-END flow• Physical Level Design is part of the BACK-END flow– Physical Design is also known as “Place and Route”• CAD tools are involved in all stages of VLSI design flow– Different tools can be used at different stages due to EDA common data formats*• Synopsys® CAD tool for Physical Design is called Astro™Front-End Design FlowFront-End Design FlowSynthesis using Design CompilerWireload model basics (1)Wireload model basics (2)Back-End Design FlowBack-End Design FlowPhysical Level Design using Synopsys®What does Astro™ do?Where does the Gate Level Netlist come from?1stInput to Astro™Standard Cell Library2ndInput to Astro™• Pre-designed collection of logic functions– OR, AND, XOR, etc• Contains both Layout and Abstract views– Layout (CEL) contains drawn mask layers required for fabrication– Abstract (FRAM) contains only
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