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MASON ECE 448 - Lecture 5 Behavioral Design Style

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Behavioral Design Style: Registers, Counters, Shift Registers Basic TestbenchesRequired readingOptional ReadingSlide 4What is a PROCESS?Anatomy of a ProcessStatement PartPROCESS with a SENSITIVITY LISTProcesses in VHDLSlide 10Component Equivalent of a ProcessVHDL Design StylesSlide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Shift registerShift Register With Parallel LoadSlide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41ConstantsConstants - featuresSlide 44Physical data typesTime values (physical literals) - ExamplesTIME valuesUnits of timeSlide 49AssertAssert - syntaxAssert - ExamplesReport - syntaxReport - ExamplesSlide 55Generating selected values of one inputGenerating all values of one inputSlide 58Generating periodical signals, such as clocksGenerating one-time signals, such as resetsTypical errorWait for vs. WaitGenerating reports in the message windowSlide 64Sequential Statements (1)Sequential Statements (2)Sequential Statements (3)George Mason University ECE 448 – FPGA and ASIC Design with VHDLBehavioral Design Style: Registers, Counters, Shift RegistersBasic Testbenches ECE 448Lecture 52 ECE 448 – FPGA and ASIC Design with VHDLRequired reading• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 7, Flip-Flops, Registers, Counters, and a Simple Processor (7.14 optional)3 ECE 448 – FPGA and ASIC Design with VHDLOptional Reading• Sundar Rajan, Essential VHDL: RTL Synthesis Done RightChapter 4, Registers and LatchesChapter 5, Counters and Simple Arithmetic Functions (see errata at http://www.vahana.com/bugs.htm)4 ECE 448 – FPGA and ASIC Design with VHDLBehavioral Design Style:Registers & Counters5 ECE 448 – FPGA and ASIC Design with VHDL•A process can be given a unique name using an optional LABEL•This is followed by the keyword PROCESS•The keyword BEGIN is used to indicate the start of the process•All statements within the process are executed SEQUENTIALLY. Hence, the order of statements is important.•A process must end with the keywords END PROCESS.testing: PROCESS BEGINtest_vector<=“00”;WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;test_vector<=“10”;WAIT FOR 10 ns;test_vector<=“11”;WAIT FOR 10 ns;END PROCESS;•A process is a sequence of instructions referred to as sequential statements.What is a PROCESS?The keyword PROCESS6 ECE 448 – FPGA and ASIC Design with VHDLAnatomy of a Process[label:] PROCESS [(sensitivity list)] [declaration part]BEGIN statement partEND PROCESS [label];OPTIONAL7 ECE 448 – FPGA and ASIC Design with VHDLStatement Part•Contains Sequential Statements to be Executed Each Time the Process Is Activated•Analogous to Conventional Programming Languages8 ECE 448 – FPGA and ASIC Design with VHDLPROCESS with a SENSITIVITY LIST•List of signals to which the process is sensitive.•Whenever there is an event on any of the signals in the sensitivity list, the process fires.•Every time the process fires, it will run in its entirety.•WAIT statements are NOT ALLOWED in a processes with SENSITIVITY LIST.label: process (sensitivity list) declaration part begin statement part end process;9 ECE 448 – FPGA and ASIC Design with VHDLProcesses in VHDL•Processes Describe Sequential Behavior•Processes in VHDL Are Very Powerful Statements•Allow to define an arbitrary behavior that may be difficult to represent by a real circuit•Not every process can be synthesized•Use Processes with Caution in the Code to Be Synthesized•Use Processes Freely in Testbenches10 ECE 448 – FPGA and ASIC Design with VHDLUse of Processes in the Synthesizable Code11 ECE 448 – FPGA and ASIC Design with VHDLComponent Equivalent of a Process•All signals which appear on the left of signal assignment statement (<=) are outputs e.g. y, z•All signals which appear on the right of signal assignment statement (<=) or in logic expressions are inputs e.g. w, a, b, c•All signals which appear in the sensitivity list are inputs e.g. clk•Note that not all inputs need to be included in the sensitivity listpriority: PROCESS (clk)BEGINIF w(3) = '1' THENy <= "11" ;ELSIF w(2) = '1' THEN y <= "10" ;ELSIF w(1) = c THENy <= a and b;ELSEz <= "00" ;END IF ;END PROCESS ;wayzprioritybcclk12 ECE 448 – FPGA and ASIC Design with VHDLVHDL Design StylesComponents andinterconnectsstructuralVHDL Design StylesdataflowConcurrent statementsbehavioralRegisters & countersSequential statements13 ECE 448 – FPGA and ASIC Design with VHDLRegisters14 ECE 448 – FPGA and ASIC Design with VHDLClock D 0 1 1 – 0 1 0 1 Truth table Graphical symbolt 1 t 2 t 3 t 4 TimeClock D Q Timing diagramQ(t+1)Q(t)D latchD Q Clock15 ECE 448 – FPGA and ASIC Design with VHDLClk D   0 1 0 1 Truth table t 1 t 2 t 3 t 4 TimeClock D Q Timing diagramQ(t+1)Q(t)D flip-flopD Q Clock Graphical symbol0 – Q(t)1 –16 ECE 448 – FPGA and ASIC Design with VHDLLIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY latch IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END latch ;ARCHITECTURE Behavior OF latch IS BEGINPROCESS ( D, Clock ) BEGINIF Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior; D latchD Q Clock17 ECE 448 – FPGA and ASIC Design with VHDLLIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior_1 OF flipflop IS BEGINPROCESS ( Clock ) BEGIN IF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior_1 ; D flip-flopD Q Clock18 ECE 448 – FPGA and ASIC Design with VHDLLIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior_2 OF flipflop IS BEGINPROCESSBEGIN WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ; END PROCESS ; END Behavior_2 ; D flip-flopD Q Clock19 ECE 448 – FPGA and ASIC Design with VHDLLIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ;ARCHITECTURE Behavior OF flipflop IS BEGINPROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ;END Behavior ; D flip-flop with asynchronous resetD Q Clock Resetn20 ECE 448 – FPGA and ASIC Design with VHDLLIBRARY ieee ; USE ieee.std_logic_1164.all


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