FSM Examples: Serial Adder, The Arbiter CircuitRequired readingOptional ReadingSlide 4Mixed Style ModelingSlide 6Serial Adder – block diagramSerial adder FSM – Mealy state diagramLeft-to-right Shift Register (1)Left-to-right Shift Register (2)Serial Adder – Entity declarationSerial Adder – Architecture (2)Serial Adder – Architecture (3)Slide 14Serial Adder – Architecture (4)Serial Adder – Architecture (5)Slide 17Slide 18Serial Adder FSM – Mealy state tableSerial Adder FSM – Mealy state-assigned tableSerial Adder - Mealy FSM CircuitSerial Adder FSM – Moore state diagramSerial Adder FSM – Moore state tableSerial Adder FSM – Moore state-assigned tableSerial Adder FSM CircuitSlide 26Slide 27The Arbiter Circuit – Moore state diagramThe Arbiter Circuit – Alternative descriptionIncorrect VHDL code for the grant signalsCorrect VHDL code for the grant signalsSimulation results for the Arbiter CircuitGeorge Mason University ECE 448 – FPGA and ASIC Design with VHDLFSM Examples:Serial Adder, The Arbiter Circuit ECE 448Lecture 92 ECE 448 – FPGA and ASIC Design with VHDLRequired reading• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 8, Synchronous Sequential Circuits Sections 8.5, 8.83 ECE 448 – FPGA and ASIC Design with VHDLOptional Reading• Sundar Rajan, Essential VHDL: RTL Synthesis Done RightChapter 6, Finite State Machines4 ECE 448 – FPGA and ASIC Design with VHDLMixing Design Styleswithin a Single Architecture5 ECE 448 – FPGA and ASIC Design with VHDLarchitecture ARCHITECTURE_NAME of ENTITY_NAME is •Here you can declare signals, constants, functions, procedures…•Component declarationsbeginConcurrent statements:•Concurrent simple signal assignment •Conditional signal assignment •Selected signal assignment•Generate statement•Component instantiation statement•Process statement•inside process you can use only sequential statementsend ARCHITECTURE_NAME;Mixed Style ModelingConcurrent Statements6 ECE 448 – FPGA and ASIC Design with VHDLSerial Adder7 ECE 448 – FPGA and ASIC Design with VHDLSerial Adder – block diagramSum A B + = Shift registerShift registerAdder FSM Shift registerB A a b s Clock8 ECE 448 – FPGA and ASIC Design with VHDLSerial adder FSM – Mealy state diagramG 00 1 ¤ 11 1 ¤ 10 0 ¤ 01 0 ¤ H 10 1 ¤ 01 1 ¤ 00 0 ¤ carry-in 0 = carry-in 1 = G:H:Reset 11 0 ¤ ab s ¤ ( )9 ECE 448 – FPGA and ASIC Design with VHDLLeft-to-right Shift Register (1)LIBRARY ieee ;USE ieee.std_logic_1164.all ;-- left-to-right shift register with parallel load and enableENTITY shiftrne ISGENERIC ( N : INTEGER := 4 ) ;PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; L, E, w : IN STD_LOGIC ; Clock : IN STD_LOGIC ; Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;END shiftrne ;10 ECE 448 – FPGA and ASIC Design with VHDLLeft-to-right Shift Register (2)ARCHITECTURE Behavior OF shiftrne ISBEGINPROCESSBEGINWAIT UNTIL Clock'EVENT AND Clock = '1' ;IF E = '1' THEN IF L = '1' THENQ <= R ; ELSEGenbits: FOR i IN 0 TO N-2 LOOP Q(i) <= Q(i+1) ; END LOOP ;Q(N-1) <= w ; END IF ;END IF ;END PROCESS ;END Behavior ;11 ECE 448 – FPGA and ASIC Design with VHDLSerial Adder – Entity declaration1 LIBRARY ieee ;2 USE ieee.std_logic_1164.all ;3 ENTITY serial IS4 GENERIC ( length : INTEGER := 8 ) ;5 PORT ( Clock : IN STD_LOGIC ;6 Reset : IN STD_LOGIC ;7 A, B : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0) ;8 Sum : BUFFER STD_LOGIC_VECTOR(length-1 DOWNTO 0));9 END serial ;12 ECE 448 – FPGA and ASIC Design with VHDLSerial Adder – Architecture (2)10 ARCHITECTURE Behavior OF serial IS11 COMPONENT shiftrne12 GENERIC ( N : INTEGER := 4 ) ;13 PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;14 L, E, w : IN STD_LOGIC ;15 Clock : IN STD_LOGIC ;16 Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;17 END COMPONENT ;18 SIGNAL QA, QB, Null_in : STD_LOGIC_VECTOR(length-1 DOWNTO 0) ;19 SIGNAL s, Low, High, Run : STD_LOGIC ;20 SIGNAL Count : INTEGER RANGE 0 TO length ;21 TYPE State_type IS (G, H) ;22 SIGNAL y : State_type ;13 ECE 448 – FPGA and ASIC Design with VHDLSerial Adder – Architecture (3)23 BEGIN24 Low <= '0' ; High <= '1' ;25 ShiftA: shiftrne GENERIC MAP (N => length)26 PORT MAP ( A, Reset, High, Low, Clock, QA ) ;27 ShiftB: shiftrne GENERIC MAP (N => length)28 PORT MAP ( B, Reset, High, Low, Clock, QB ) ;14 ECE 448 – FPGA and ASIC Design with VHDLSerial adder FSM – Mealy state diagramG 00 1 ¤ 11 1 ¤ 10 0 ¤ 01 0 ¤ H 10 1 ¤ 01 1 ¤ 00 0 ¤ carry-in 0 = carry-in 1 = G:H:Reset 11 0 ¤ ab s ¤ ( )15 ECE 448 – FPGA and ASIC Design with VHDLSerial Adder – Architecture (4)29 AdderFSM: PROCESS ( Reset, Clock )30 BEGIN31 IF Reset = '1' THEN32 y <= G ;33 ELSIF Clock'EVENT AND Clock = '1' THEN34 CASE y IS35 WHEN G =>36 IF QA(0) = '1' AND QB(0) = '1' THEN y <= H ;37 ELSE y <= G ;38 END IF ;39 WHEN H =>40 IF QA(0) = '0' AND QB(0) = '0' THEN y <= G ;41 ELSE y <= H ;42 END IF ;43 END CASE ;44 END IF ;45 END PROCESS AdderFSM ;16 ECE 448 – FPGA and ASIC Design with VHDLSerial Adder – Architecture (5)46 WITH y SELECT47 s <= QA(0) XOR QB(0) WHEN G,48 NOT ( QA(0) XOR QB(0) ) WHEN H ;49 Null_in <= (OTHERS => '0') ;50 ShiftSum: shiftrne GENERIC MAP ( N => length )51 PORT MAP ( Null_in, Reset, Run, s, Clock, Sum ) ;17 ECE 448 – FPGA and ASIC Design with VHDLSerial Adder – Architecture (5)52 Stop: PROCESS53 BEGIN54 WAIT UNTIL (Clock'EVENT AND Clock = '1') ;55 IF Reset = '1' THEN56 Count <= length ;57 ELSIF Run = '1' THEN58 Count <= Count -1 ;59 END IF ;60 END PROCESS ;61 Run <= '0' WHEN Count = 0 ELSE '1' ; -- stops counter and ShiftSum62 END Behavior ;18 ECE 448 – FPGA and ASIC Design with VHDLSerial adder FSM – Mealy state diagramG 00 1 ¤ 11 1 ¤ 10 0 ¤ 01 0 ¤ H 10 1 ¤ 01 1 ¤ 00 0 ¤ carry-in 0 = carry-in 1 = G:H:Reset 11 0 ¤ ab s ¤ ( )19 ECE 448 – FPGA and ASIC Design with VHDLSerial Adder FSM – Mealy state tablePresent Next state Outputs state ab=00 01 10 11 00 01 10 11G G G G H 0 1 1 0 H G H H H 1 0 0 120 ECE 448 – FPGA and ASIC Design with VHDLSerial Adder FSM – Mealy state-assigned tablePresent Next state Outputstate ab=00 01 10 11 00 01 10 11y Y s 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 121 ECE 448 – FPGA and ASIC Design with VHDLSerial Adder - Mealy FSM CircuitFulladderabsDQQcarry-outClockResetY y22 ECE 448 – FPGA and ASIC Design with
View Full Document
Unlocking...