MASON ECE 448 - Lecture 9 FSM Examples: Serial Adder, The Arbiter Circuit (32 pages)

Previewing pages 1, 2, 15, 16, 31, 32 of 32 page document View the full content.
View Full Document

Lecture 9 FSM Examples: Serial Adder, The Arbiter Circuit



Previewing pages 1, 2, 15, 16, 31, 32 of actual document.

View the full content.
View Full Document
View Full Document

Lecture 9 FSM Examples: Serial Adder, The Arbiter Circuit

80 views

Lecture Notes


Pages:
32
School:
George Mason University
Course:
Ece 448 - FPGA and ASIC Design with VHDL
FPGA and ASIC Design with VHDL Documents

Unformatted text preview:

ECE 448 Lecture 9 FSM Examples Serial Adder The Arbiter Circuit ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 8 Synchronous Sequential Circuits Sections 8 5 8 8 ECE 448 FPGA and ASIC Design with VHDL 2 Optional Reading Sundar Rajan Essential VHDL RTL Synthesis Done Right Chapter 6 Finite State Machines ECE 448 FPGA and ASIC Design with VHDL 3 Mixing Design Styles within a Single Architecture ECE 448 FPGA and ASIC Design with VHDL 4 Mixed Style Modeling architecture ARCHITECTURE NAME of ENTITY NAME is Here you can declare signals constants functions procedures Component declarations begin Concurrent statements Concurrent simple signal assignment Conditional signal assignment Selected signal assignment Generate statement Concurrent Statements Component instantiation statement Process statement inside process you can use only sequential statements end ARCHITECTURE NAME ECE 448 FPGA and ASIC Design with VHDL 5 Serial Adder ECE 448 FPGA and ASIC Design with VHDL 6 Serial Adder block diagram A a Shift register Adder FSM s Shift register Shift register b Sum A B B Clock ECE 448 FPGA and ASIC Design with VHDL 7 Serial adder FSM Mealy state diagram Reset 00 0 01 1 10 1 ab s 11 0 G H 01 0 10 0 11 1 00 1 G carry in 0 H carry in 1 ECE 448 FPGA and ASIC Design with VHDL 8 Left to right Shift Register 1 LIBRARY ieee USE ieee std logic 1164 all left to right shift register with parallel load and enable ENTITY shiftrne IS GENERIC N INTEGER 4 PORT R IN STD LOGIC VECTOR N 1 DOWNTO 0 L E w IN STD LOGIC Clock IN STD LOGIC Q BUFFER STD LOGIC VECTOR N 1 DOWNTO 0 END shiftrne ECE 448 FPGA and ASIC Design with VHDL 9 Left to right Shift Register 2 ARCHITECTURE Behavior OF shiftrne IS BEGIN PROCESS BEGIN WAIT UNTIL Clock EVENT AND Clock 1 IF E 1 THEN IF L 1 THEN Q R ELSE Genbits FOR i IN 0 TO N 2 LOOP Q i Q i 1 END LOOP Q N 1 w END IF END IF END PROCESS END Behavior ECE 448 FPGA



View Full Document

Access the best Study Guides, Lecture Notes and Practice Exams

Loading Unlocking...
Login

Join to view Lecture 9 FSM Examples: Serial Adder, The Arbiter Circuit and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Lecture 9 FSM Examples: Serial Adder, The Arbiter Circuit and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?