DOC PREVIEW
MASON ECE 448 - Lecture 15 Advanced Testbenches

This preview shows page 1-2-14-15-30-31 out of 31 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 31 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 31 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 31 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 31 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 31 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 31 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 31 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

Slide 1SourcesSlide 3Records – Examples (1)Records – Examples (2)Slide 6AssertAssert - syntaxAssert - ExamplesReport - syntaxReport - ExamplesSlide 12Testbench (1)Testbench (2)Testbench (3)Testbench (4)Testbench (5)Slide 18Design Under Test (1)Design Under Test (2)Test vector file (1)Test vector file (2)Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Testbench (6)Testbench (7)Hex formatGeorge Mason University ECE 448 – FPGA and ASIC Design with VHDLECE 448Lecture 15Advanced Testbenches2 ECE 448 – FPGA and ASIC Design with VHDLSources•Sundar Rajan, Essential VHDL: RTL Synthesis Done RightChapter 14, starting from “Design Verification” (handout distributed in class)3 ECE 448 – FPGA and ASIC Design with VHDLRecords4 ECE 448 – FPGA and ASIC Design with VHDLRecords – Examples (1)type opcodes is (add, sub, and, or);type reg_number is range 0 to 8;type instruction is recordopcode: opcodes;source_reg1: reg_number;source_reg2: reg_number;dest_reg: reg_number;displacement: integer;end record instruction5 ECE 448 – FPGA and ASIC Design with VHDLRecords – Examples (2)type word is recordinstr: instruction;data: bit_vector(31 downto 0);end record instruction;constant add_instr_1_3: instruction:=(opcode => add, source_reg1 | dest_reg => 1, source_reg2 => 3, displacement => 0);6 ECE 448 – FPGA and ASIC Design with VHDLAsserts & Reports7 ECE 448 – FPGA and ASIC Design with VHDLAssertAssert is a non-synthesizable statementwhose purpose is to write out messageson the screen when problems are foundduring simulation.Depending on the severity of the problem,The simulator is instructed to continuesimulation or halt.8 ECE 448 – FPGA and ASIC Design with VHDLAssert - syntaxASSERT condition[REPORT "message"[SEVERITY severity_level ];The message is written when the condition is FALSE.Severity_level can be: Note, Warning, Error (default), or Failure.9 ECE 448 – FPGA and ASIC Design with VHDLAssert - Examplesassert initial_value <= max_value report "initial value too large" severity error;assert packet_length /= 0 report "empty network packet received" severity warning;assert false report "Initialization complete" severity „note”;10 ECE 448 – FPGA and ASIC Design with VHDLReport - syntaxREPORT "message"[SEVERITY severity_level ];The message is always written.Severity_level can be: Note (default), Warning, Error, or Failure.11 ECE 448 – FPGA and ASIC Design with VHDLReport - Examplesreport "Initialization complete";report "Current time = " & time'image(now);report "Incorrect branch" severity error;12 ECE 448 – FPGA and ASIC Design with VHDLUsing Arrays of Test VectorsIn Testbenches13 ECE 448 – FPGA and ASIC Design with VHDLTestbench (1)LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY sevenSegmentTB isEND sevenSegmentTB;ARCHITECTURE testbench OF sevenSegmentTB ISCOMPONENTsevenSegment PORT ( bcdInputs : IN STD_LOGIC_VECTOR (3 DOWNTO 0); seven_seg_outputs : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); );end COMPONENT;CONSTANT PropDelay: time := 40 ns;CONSTANT SimLoopDelay: time := 10 ns;14 ECE 448 – FPGA and ASIC Design with VHDLTestbench (2)TYPE vector IS RECORD bcdStimulus: STD_LOGIC_VECTOR(3 downto 0); sevSegOut: STD_LOGIC_VECTOR(6 downto 0);END RECORD;CONSTANT NumVectors: INTEGER:= 10;TYPE vectorArray is ARRAY (0 TO NumVectors - 1) OF vector;CONSTANT vectorTable: vectorArray := ( (bcdStimulus => "0000", sevSegOut => "0000001"), (bcdStimulus => "0001", sevSegOut => "1001111"), (bcdStimulus => "0010", sevSegOut => "0010010"), (bcdStimulus => "0011", sevSegOut => "0000110"), (bcdStimulus => "0100", sevSegOut => "1001100"), (bcdStimulus => "0101", sevSegOut => "0100100"), (bcdStimulus => "0110", sevSegOut => "0100000"), (bcdStimulus => "0111", sevSegOut => "0001111"), (bcdStimulus => "1000", sevSegOut => "0000000"), (bcdStimulus => "1001", sevSegOut => "0000100"));15 ECE 448 – FPGA and ASIC Design with VHDLTestbench (3)SIGNAL StimInputs: STD_LOGIC_VECTOR(3 downto 0);SIGNAL CaptureOutputs: STD_LOGIC_VECTOR(6 downto 0);BEGIN u1: sevenSegment PORT MAP (bcdInputs => StimInputs,seven_seg_outputs => CaptureOutputs);16 ECE 448 – FPGA and ASIC Design with VHDLTestbench (4)LoopStim: PROCESSBEGIN FOR i in 0 TO NumVectors-1 LOOP StimInputs <= vectorTable(i).bcdStimulus; WAIT FOR PropDelay; ASSERT CaptureOutputs == vectorTable(i).sevSegOut REPORT “Incorrect Output” SEVERITY error;WAIT FOR SimLoopDelay; END LOOP;17 ECE 448 – FPGA and ASIC Design with VHDLTestbench (5)WAIT; END PROCESS;END testbench;18 ECE 448 – FPGA and ASIC Design with VHDLFile I/O19 ECE 448 – FPGA and ASIC Design with VHDLDesign Under Test (1)LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;ENTITY loadCnt IS PORT ( data: IN STD_LOGIC_VECTOR (7 DOWNTO 0); load: IN STD_LOGIC; clk: IN STD_LOGIC; rst: IN STD_LOGIC; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) );END loadCnt;20 ECE 448 – FPGA and ASIC Design with VHDLDesign Under Test (2)ARCHITECTURE rtl OF loadCnt ISSIGNAL cnt: STD_LOGIC_VECTOR (7 DOWNTO 0);BEGIN counter: PROCESS (clk, rst) BEGIN IF (rst = '1') THEN cnt <= (OTHERS => '0'); ELSIF (clk'event AND clk = '1') THEN IF (load = '1') THEN cnt <= data; ELSE cnt <= cnt + 1; END IF; END IF; END PROCESS; q <= cnt;END rtl;21 ECE 448 – FPGA and ASIC Design with VHDLTest vector file (1)#Format is Rst, Load, Data, Q#load the counter to all 1s0 1 11111111 11111111#reset the counter1 0 10101010 00000000#now perform load/increment for each bit0 1 11111110 111111100 0 11111110 11111111#0 1 11111101 111111010 0 11111101 11111110#0 1 11111011 111110110 0 11111011 11111100#0 1 11110111 111101110 0 11110111 1111100022 ECE 448 – FPGA and ASIC Design with VHDLTest vector file (2)#0 1 11101111 111011110 0 11101111 11110000#0 1 11011111 110111110 0 11011111 11100000#0 1 10111111 101111110 0 10111111 11000000#0 1 01111111 011111110 0 01111111 10000000##check roll-over case0 1 11111111 111111110 0 11111111 00000000## End vectors23 ECE 448 – FPGA and ASIC Design with VHDLTestbench (1)LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_textio.all;LIBRARY std;USE std.textio.all;ENTITY loadCntTB ISEND loadCntTB;24 ECE 448 – FPGA and ASIC Design with VHDLTestbench (2)ARCHITECTURE testbench OF loadCntTB ISCOMPONENT loadCnt PORT ( data: IN STD_LOGIC_VECTOR (7 DOWNTO 0); load: IN STD_LOGIC; clk: IN STD_LOGIC; rst: IN STD_LOGIC;


View Full Document

MASON ECE 448 - Lecture 15 Advanced Testbenches

Documents in this Course
Load more
Download Lecture 15 Advanced Testbenches
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Lecture 15 Advanced Testbenches and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Lecture 15 Advanced Testbenches 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?