IntroductionPast FPGA to ASIC ComparisonsNew FPGA to ASIC ComparisonBenchmark SelectionFPGA CAD FlowASIC CAD FlowASIC SynthesisASIC Placement and RoutingExtraction and Timing AnalysisComparison Metrics and Measurement MethodAreaSpeedPowerDynamic and Static Power MeasurementDynamic and Static Power Comparison MethodologyResultsAreaSpeedPower ConsumptionConclusionAcknowledgementsREFERENCES -9ptMeasuring the Gap Between FPGAs and ASICsIan Kuon and Jonathan RoseThe Edward S. Rogers Sr. Department of Electrical and Computer EngineeringUniversity of TorontoToronto, ON{ikuon,jayar}@eecg.utoronto.caABSTRACTThis paper presents experimental measurements of the dif-ferences between a 90nm CMOS FPGA and 90nm CMOSStandard Cell ASICs in terms of logic density, circuit speedand power consumption. We are motivated to make thesemeasurements to enable system designers to make better in-formed choices between these two media and to give insightto FPGA makers on the deficiencies to attack and therebyimprove FPGAs. In the paper, we describe the methodologyby which the measurements were obtained and we show that,for circuits containing only combinational logic and flip-flops, the ratio of silicon area required to implement them inFPGAs and ASICs is on average 40. Modern FPGAs alsocontain “hard” blocks such as multiplier/accumulators andblock memories and we find that these blocks reduce thisaverage area gap significantly to as little as 21. The ratioof critical path delay, from FPGA to ASIC, is roughly 3 to4, with less influence from block memory and hard multipli-ers. The dynamic power consumption ratio is approximately12 times and, with hard blocks, this gap generally becomessmaller.Categories and Subject DescriptorsB.7 [Integrated Circuits]: Types and Design StylesGeneral TermsDesign, Performance, MeasurementKeywordsFPGA, ASIC, Area Comparison, Delay Comparison, PowerComparison1. INTRODUCTIONWe were motivated to measure the area, performance andpower consumption gap between field-programmable gatearrays (FPGAs) and standard cell application-specific inte-grated circuits (ASICs) for the following reasons:Permission to make digital or hard copies of all or part of this work forpersonal or classroom use is granted without fee provided that copies arenot made or distributed for profit or commercial advantage and that copiesbear this notice and the full citation on the first page. To copy otherwise, torepublish, to post on servers or to redistribute to lists, requires prior specificpermission and/or a fee.FPGA’06, February 22–24, 2006, Monterey, California, USA.Copyright 2006 ACM 1-59593-292-5/06/0002 ...$5.00.1. In the early stages of system design, when system ar-chitects choose their implementation medium, they of-ten choose between FPGAs and ASICs. Such decisionsare based on the differences in cost (which is related toarea), performance and power consumption betweenthese implementation media but to date there havebeen few attempts to quantify these differences. Asystem architect can use these measurements to as-sess whether implementation in an FPGA is feasible.These measurements can also be useful for those build-ing ASICs that contain programmable logic, by quan-tifying the impact of leaving part of a design to beimplemented in the programmable fabric.2. FPGA makers seeking to improve FPGAs can gain in-sight by quantitative measurements of these metrics,particularly when it comes to understanding the bene-fit of less programmable (but more efficient) hard het-erogeneous blocks such as block memory [3, 17, 28]multipliers/accumulators [3, 17, 28] and multiplexers[28] that modern FPGAs often employ.In this paper we focus on a comparison between a 90 nmCMOS SRAM-programmable FPGA and a 90 nm CMOSstandard cell technology. We chose an SRAM-based FPGAbecause that approach by far dominates the market, and itwas necessary to limit the scope of comparison in order tomake this work tractable. Similarly, standard cells [8, 21]are currently the dominant choice in ASIC implementationsversus pure gate arrays and the newer “structured ASIC”platforms [18, 19].We present these measurements knowing that some of themethodology used will be controversial. We will carefullydescribe the comparison process so that readers can formtheir own opinions of the validity of the result. As always,the set of benchmarks we use are highly influential on theresults, and indeed any given FPGA vs. ASIC comparisoncan vary significantly based on the application, as our resultsshow. Since we perform measurements using a large set ofdesigns, it was not feasible to individually optimize each de-sign and it is likely that manual optimizations or greatertuning of the tools could yield improved results for any in-dividual design; however, this is true for both the ASIC andFPGA platforms. We believe our results are more meaning-ful than past comparisons because we do consider a rangeof benchmarks instead of focusing on just a single design ashas been done in most past analyses.This paper is organized as follows: Section 2 describesprevious work on measuring the gap between FPGAs andASICs. Section 3 details the experimental methodology we21use in this work. The approach is a fundamentally empiricalone in which the same circuits are implemented throughtwo computer-aided design (CAD) flows which are describedin Sections 4 and 5. Section 6 gives a precise definition ofthe comparison metrics. Section 7 presents the comparisonresults, and Section 8 concludes the paper.2. PAST FPGA TO ASIC COMPARISONSThere have been a small number of past attempts to quan-tify the gap between FPGAs and ASICs which we will reviewhere.One of the earliest statements quantifying the gap be-tween FPGAs and pre-fabricated media was by Brown etal. [4]. That work reported the logic density gap betweenFPGAs and Mask-programmable Gate Arrays (MPGAs) tobe between 8 to 12 times, and the circuit performance gapto be approximately a factor of 3. The basis for these num-bers was a cursory comparison of the largest available gatecounts in each technology, and the anecdotal reports of theapproximate operating frequencies in the two technologiesat the time. While the latter may have been reasonable, theformer suffered from optimistic gate counting in FPGAs.In this paper we are seeking to measure the gap againststandard cell implementations, rather than the less com-mon MPGA. MPGAs have lower density relative to stan-dard cells, which are on the order of
View Full Document
Unlocking...