Midterm ExamECE 448Spring 2007Tuesday Section(15 points)InstructionsZip all your deliverables into an archive <last_name>.zip and submit it through WebCT no later than Tuesday, March 20, 10:30 PM EST.IntroductionDesign a digital system that will compute a median for a set of three data inputs of the size of Nbits each. The three data inputs are clocked in serially beginning at the high value of the signalSTART. The median value is generated at the output at the same time as the DONE signal. Resetsignal is asynchronous. CLK period is 10ns for simulation. All registers are active on the risingedge of the clock. Assume the default value of N = 8.The pseudocode for computing the median of three values DATA_IN(1), DATA_IN(2) andDATA_IN(3) is given below: D=DATA_IN(1) DMAX = DD=DATA_IN(2)if D>DMAX then DMED = DMAX DMAX = Delse DMED = Dend ifD=DATA_IN(3)if D>DMAX then DMED = DMAX DMAX = Delsif D > DMED DMED = Dend ifMEDIAN = DMEDDMAX denotes current maximumDMED denotes current second valueThe interface of the circuit is shown below: MEDIAN DATA_IN N N Median Function CLK RESET START DONESignal Mode Size(bits)FunctionCLK Input 1 10ns, 50% duty cycle master clockRESET Input 1 Asynchronous resetSTART Input 1 Starts the computation cycle, active high for 1 clock cycleDATA_IN Input N Inputs data points serially for 3 consecutive clock cycles beginning at the high value of the START signalMEDIAN Output N Outputs median pointDONE Output 1 Signals the end of the computation. Output is valid on this signal. This signal also clears both Max and Med registers to get ready for the next computation.The execution unit of the circuit is described belowThe timing waveform is shown below for N = 4LTmedLTmax0110Max_Reg Med_RegN NNDATA_INMEDIANCLKSTARTRESETFSMDONEInput > RegisterInput > Register01Design Requirements The combinational portion of the circuit should be described using the dataflow VHDLcode, and the sequential portion of the circuit should be described using the synthesizablebehavioral code. Your code should infer a circuit that requires a minimum amount ofFPGA resources. The target clock frequency should be 100 MHz. Tasks Perform the following tasks: 1. Write a VHDL code of the execution unit of the described above circuit (shown in theblock diagram above). 2. Write a testbench verifying the operation of your execution unit for the case of N=8. 3. Perform functional simulation of your circuit and use it to debug your VHDL code. 4. Design a control unit of your circuit. If you do not know how to do it, go to Step 6.5. Write a testbench verifying the operation of your entire code for the case of N=8.6. Synthesize your circuit using Synplify Pro for the case of N=8. Save the RTLschematic. 7. Implement your circuit using Xilinx ISE. 8. Perform timing simulations of your circuit using Active-HDL. 9. Run the static timing analysis of your circuit. 10. Based on the circuit block diagram and the implementation reports, determine themost critical path in your circuit and its length. Deliverables 1. VHDL code of your entire circuit fulfilling the requirements specified in the DesignRequirements section above 2. VHDL code of your testbenches 3. RTL schematic of your circuit 4. Timing waveforms from the functional simulation demonstrating the correct operationof your circuit. 5. Description of the critical path in your circuit 6. Timing waveforms from the timing simulation demonstrating the delay of the circuitmost critical path 7. FPGA resource utilization 8. Minimum clock period of your
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