Modeling of Circuits with a Regular Structure Mixing Design Styles SynthesisRequired readingSlide 3Slide 4For Generate StatementSlide 6PARITY: Block DiagramPARITY: Entity DeclarationSlide 9PARITY: ArchitecturePARITY: Block Diagram (2)Slide 12PARITY: Architecture (2)Slide 14Slide 15Slide 16Example 1A 4-to-1 MultiplexerStraightforward code for Example 1Slide 20Modified code for Example 1Slide 22Example 2A 2-to-4 binary decoderVHDL code for Example 2 (1)VHDL code for Example 2 (2)Slide 27Example 3: Variable rotator - InterfaceBlock diagramVHDL code for a 16-bit 2-to-1 MultiplexerFixed rotationFixed rotation by L positionsVHDL code for for a fixed 16-bit rotatorStructural VHDL code for for a variable 16-bit rotator (1)Structural VHDL code for for a variable 16-bit rotator (2)Structural VHDL code for for a variable 16-bit rotator (3)Slide 37ConstantsConstants - featuresSlide 40Explicit Component Declaration versus PackageExplicit Component Declaration TipsMETHOD #2: Package component declarationPackagesPackage – example (1)Package – example (2)Package – example (3)Package usage (1)Package usage (2)Aldec Compilation OrderSlide 51VHDL Design StylesMixed Style ModelingPRNG Example (1)PRNG Example (2)SynthesisResources & Required ReadingDesign flow (1)Synthesis ToolsSlide 60Features of synthesis toolsTiming report after synthesisGeorge Mason University ECE 448 – FPGA and ASIC Design with VHDL Modeling of Circuits with a RegularStructureMixing Design StylesSynthesisECE 448Lecture 122 ECE 448 – FPGA and ASIC Design with VHDLRequired reading• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL DesignChapter 6.6.4, Generate StatementsChapter A.7.5, Generate StatementChapter A.10.9, Using Subcircuits with Generic ParametersChapter A.11, Common Errors in VHDL Code3 ECE 448 – FPGA and ASIC Design with VHDLGenerate schemefor equations4 ECE 448 – FPGA and ASIC Design with VHDLData-flow VHDL• concurrent signal assignment ( )• conditional concurrent signal assignment (when-else)• selected concurrent signal assignment (with-select-when)• generate scheme for equations (for-generate)Major instructionsConcurrent statements5 ECE 448 – FPGA and ASIC Design with VHDLFor Generate StatementFor - Generatelabel: FOR identifier IN range GENERATE BEGIN {Concurrent Statements} END GENERATE;6 ECE 448 – FPGA and ASIC Design with VHDLPARITY Example7 ECE 448 – FPGA and ASIC Design with VHDLPARITY: Block Diagram8 ECE 448 – FPGA and ASIC Design with VHDLPARITY: Entity DeclarationLIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC );END parity;9 ECE 448 – FPGA and ASIC Design with VHDLPARITY: Block Diagramxor_out(1)xor_out(2)xor_out(3)xor_out(4)xor_out(5)xor_out(6)10 ECE 448 – FPGA and ASIC Design with VHDLPARITY: ArchitectureARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: std_logic_vector (6 downto 1);BEGINxor_out(1) <= parity_in(0) XOR parity_in(1);xor_out(2) <= xor_out(1) XOR parity_in(2);xor_out(3) <= xor_out(2) XOR parity_in(3);xor_out(4) <= xor_out(3) XOR parity_in(4);xor_out(5) <= xor_out(4) XOR parity_in(5);xor_out(6) <= xor_out(5) XOR parity_in(6);parity_out <= xor_out(6) XOR parity_in(7);END parity_dataflow;11 ECE 448 – FPGA and ASIC Design with VHDLPARITY: Block Diagram (2)xor_out(1)xor_out(2)xor_out(3)xor_out(4)xor_out(5)xor_out(6)xor_out(7)xor_out(0)12 ECE 448 – FPGA and ASIC Design with VHDLPARITY: ArchitectureARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 downto 0);BEGINxor_out(0) <= parity_in(0);xor_out(1) <= xor_out(0) XOR parity_in(1);xor_out(2) <= xor_out(1) XOR parity_in(2);xor_out(3) <= xor_out(2) XOR parity_in(3);xor_out(4) <= xor_out(3) XOR parity_in(4);xor_out(5) <= xor_out(4) XOR parity_in(5);xor_out(6) <= xor_out(5) XOR parity_in(6);xor_out(7) <= xor_out(6) XOR parity_in(7);parity_out <= xor_out(7);END parity_dataflow;13 ECE 448 – FPGA and ASIC Design with VHDLPARITY: Architecture (2)ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0);BEGINxor_out(0) <= parity_in(0);G2: FOR i IN 1 TO 7 GENERATExor_out(i) <= xor_out(i-1) XOR parity_in(i);END GENERATE G2; parity_out <= xor_out(7);END parity_dataflow;14 ECE 448 – FPGA and ASIC Design with VHDLGenerate schemefor components15 ECE 448 – FPGA and ASIC Design with VHDLStructural VHDL• component instantiation (port map)• component instantiation with generic (generic map, port map)• generate scheme for component instantiations (for-generate)Major instructions16 ECE 448 – FPGA and ASIC Design with VHDLExample 117 ECE 448 – FPGA and ASIC Design with VHDLw 8 w 11s 1 w 0 s 0 w 3 w 4 w 7 w 12w 15s 3 s 2 f Example 118 ECE 448 – FPGA and ASIC Design with VHDLA 4-to-1 MultiplexerLIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY mux4to1 ISPORT ( w0, w1, w2, w3 : IN STD_LOGIC ;s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;f : OUT STD_LOGIC ) ;END mux4to1 ;ARCHITECTURE Dataflow OF mux4to1 ISBEGINWITH s SELECTf <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ;END Dataflow ;19 ECE 448 – FPGA and ASIC Design with VHDLStraightforward code for Example 1LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY Example1 ISPORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ; s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ;END Example1 ;20 ECE 448 – FPGA and ASIC Design with VHDLStraightforward code for Example 1ARCHITECTURE Structure OF Example1 ISCOMPONENT mux4to1PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;f : OUT STD_LOGIC ) ;END COMPONENT ;SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;BEGINMux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ;Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ;Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ;Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ;Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;END Structure ;21 ECE 448 – FPGA and ASIC Design with VHDLModified code for Example 1ARCHITECTURE Structure OF Example1 ISCOMPONENT mux4to1PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;f : OUT STD_LOGIC ) ;END COMPONENT ;SIGNAL m :
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