Slide 1Slide 2IntroductionDebouncer testTop-level Circuit for Lab 3Slide 6PRNGSlide 8Slide 9Block Diagram of Lab 3 PRNGInputs of XOR gatesThree Initialization OptionsPRNG Test VectorsSlide 14DebouncerSlide 16Slide 17Slide 18Slide 19Rising Edge DetectorSlide 21Slide 22CounterSlide 24Slide 25Slide 26Clock DividerSlide 28Slide 29Basys IISlide 31Slide 32Seven Segment DisplaySlide 34Slide 35FPGA Design process (1)FPGA Design process (2)Slide 38ECE 448: Spring 11Lab 3Part 1Sequential Logic for SynthesisIntroduction: Why are we here?Part 1: Pseudorandom Random Number GeneratorsPart 2: Debouncing CircuitPart 3: Rising Edge DetectorPart 4: CounterPart 5: Clock DividerPart 6: Basys IIPart 7: FPGA Design Flow based on Aldec Active-HDLAgenda for todayIntroduction•Purpose- Test basic circuits on the Basys II–Counter–Debouncing circuit–Rising edge detector•Introduction to Pseudo-Random Number Generator (PRNG)•Introduction to FPGA Design Flow based onAldec Active-HDLDebouncer testNotation: RED – Rising Edge Detector7-Seg Display Unit15:8 7:0Genericn=8Counterrst_istep_iclk_idata_oen_i8Genericn=8Counterrst_istep_iclk_idata_oen_i8REDbutton(0)button(2) button(2)sw(3:0)zeros(7:4)8REDDEBOUNCERbutton(1)clk_50Mclk_1krst_iTop-level Circuit for Lab 3Notation: RED – Rising Edge Detector7-Seg Display Unit15:8 7:0rst_iclk_idata_oen_i8PRNGrst_iclk_idata_oen_i8REDbutton(0)button(2) button(2)DEBOUNCERclk_50Mclk_1kGenericn=8Counterrst_iPart 1Pseudo-Random Number GeneratorPRNG•Also known as Deterministic Random Bit Generator (DRBG)•Generates a sequence of numbers that approximates the properties of random numbers. •The sequence is fully deterministic, i.e., it can be repeated based on an initial state of PRNG.•The period of the sequence may be made very large (typically, 2n-1, where n is an internal state size)PRNG•Random Numbers are often important–Testing of VLSI circuits–Cryptography–Monte Carlo simulations–Noise addition–Bit error detection, and many other applicationsPRNGBlock Diagram of Lab 3 PRNGInputs of XOR gatesThree Initialization OptionsOption 1 (required): Initialization to ALL ONES, using the signal SET common to all shift registers (connected to rst_i).Option 2 (required): Initialization to ALL ONES by shifting '1’ to all shift registers for 6 clock cycles after reset.Option 3: (bonus): Initialization to arbitrary value,by shifting in internal state serially, using special input sin, one bit per clock cycle.PRNG Test VectorsClock Cycle Output1 FF2 743 BD4 675 EA6 AE7 4E8 5B9 6A10 62Clock Cycle Output11 D912 3113 8714 3815 95 16 1917 5c18 CE19 7E20 52Part 2Debouncing CircuitDebouncerCapacitance in the button and contacts “bouncing” causes spurs that cause false positives. A debouncing circuit removes these spurs.DebouncerWhen the first change is detected, we ignore all subsequent changes for some period of time, preferably until all of the bouncing would have occurred. This is usually on the order of ms.DebouncerDebouncerresetinputclkoutputDebouncerPart 3Rising Edge DetectorRising Edge Detector•Turn a step function into an impulse•Allows a step to run a circuit for only one clock cycle•Can also be used to cross clock domainsRising Edge DetectorRising Edge Detectorclk_idata_idata_odata_iclk_idata_orising edge detectorPart 4CounterCounter•Count whenever enable signal is high•Synchronous reset•Data out is valid after one clock cycle•Increment step size is configurable•Why use a generic?–Generics make circuits reusableCounterGenericnCounterrst_istep_iclk_idata_oen_innCounterRegister0 1step_ien_i clk_idata_onnnnrst_iPart 5Clock DividerClock DividerClock DividerCounter = c nrst_ienclk_iclk_odata_oen_istep_i1nPart 6Basys IIBasys IIBasys IISwitches (8)Buttons (4)7 Segment Displays (4)VGA connectorON/OFF SwitchExpansion portsLEDs (8)Basys 2 I/O CircuitsSeven Segment Display•By lighting different combinations of LEDs, different figures appear•For Instance CA, CB, CC make ‘7’•Common anode means that writing a ‘0’ to CA-DP illuminates the led, where a ‘1’ turns it offSeven Segment Display•SSRegCtrl has a 16 bit input that is divided into four 4-bit digits•AN(0:3) select which 7 segment display to output to•Digilent recommends a digit period of between 1kHz and 60HzPart 7FPGA Design Flow based on Aldec Active-HDLFPGA Design process (1)Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds…..Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; );end AES_core;Specification (Lab Assignments)VHDL description (Your Source Files)Functional simulationPost-synthesis simulationSynthesisOn-paper hardware design (Block diagram & ASM chart)FPGA Design process (2)ImplementationConfigurationTiming simulationOn chip testingDesign Process control from
View Full Document
Unlocking...