ECE 448 Lecture 19 ASIC Front End Design ECE 448 FPGA and ASIC Design with VHDL George Mason University Two competing implementation approaches ASIC Application Specific Integrated Circuit designed all the way from behavioral description to physical layout designs must be sent for expensive and time consuming fabrication in semiconductor foundry ECE 448 FPGA and ASIC Design with VHDL FPGA Field Programmable Gate Array no physical layout design design ends with a bitstream used to configure a device bought off the shelf and reconfigured by designers themselves 2 FPGAs vs ASICs ASICs High performance FPGAs Off the shelf Low development costs Low power Short time to the market Low cost but only in high volumes ECE 448 FPGA and ASIC Design with VHDL Reconfigurability 3 ASIC Design Example Factoring circuit GMU Global Memory Local Memory ECE 448 FPGA and ASIC Design with VHDL 4 ASIC 130 nm vs Virtex II 6000 Factoring GMU 19 68 mm 19 80 mm 51x Area of Xilinx Virtex II 6000 FPGA estimation by R J Lim Fong MS Thesis VPI 2004 2 7 mm 2 82 mm Area of an ASIC with equivalent functionality ECE 448 FPGA and ASIC Design with VHDL 5 ASICs vs FPGAs Source I Kuon J Rose University of Toronto Measuring the Gap Between FPGAs and ASICs IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems vol 62 no 2 Feb 2007 ECE 448 FPGA and ASIC Design with VHDL 6 ECE 448 FPGA and ASIC Design with VHDL 7 ECE 448 FPGA and ASIC Design with VHDL 8 ECE 448 FPGA and ASIC Design with VHDL 9 ECE 448 FPGA and ASIC Design with VHDL 10 Simplified ASIC Design Flow Front End Design Back End Design Synthesis Timing Analysis Floorplanning Placement Clock Tree Synthesis Routing Design for Manufacturing ECE 448 FPGA and ASIC Design with VHDL 11 31 Major ASIC Toolsets Cadence Magma ECE 448 FPGA and ASIC Design with VHDL 12 Simplified ASIC Design Flow Front End Design Back End Design Synthesis Timing Analysis Synopsys Tools Design Analyzer Primetime Floorplanning Placement Clock Tree Synthesis Astro Routing Design for Manufacturing ECE 448 FPGA and ASIC Design with VHDL 13 31 A Complete Placed and Routed Chip IP ECE 448 FPGA and ASIC Design with VHDL 14 28 What is Physical Layout VDD VDD PMOS PMOS OUT IN IN OUT NMOS NMOS GND GND Transistor or Device View Physical or Layout View Physical Layout Topography of devices and interconnects made up of polygons that represent different layers of material diffusion polysilicon metal contact etc ECE 448 FPGA and ASIC Design with VHDL 15 Process of Device Fabrication Devices are fabricated vertically on a silicon substrate wafer by layering different materials in specific locations and shapes on top of each other Each of many process masks defines the shapes and locations of a specific layer of material diffusion polysilicon metal contact etc Mask shapes derived from the layout view are transformed to silicon via photolithographic and chemical processes Silicon Substrate Layout or Mask aerial view ECE 448 FPGA and ASIC Design with VHDL Wafer cross sectional view 16 40 Wafer Representation of Layout Polygons 0 25 um PMOS Input VDD Output GND NMOS Aerial or Layout View ECE 448 FPGA and ASIC Design with VHDL Wafer Cross sectional View 17 41 Front End Design Flow ECE 448 FPGA and ASIC Design with VHDL 18 Simplified RTL Synthesis Write RTL HDL Code HDL No Simulate OK Yes Synthesize RTL Code to Gates Gate Level Netlist No Constraints Met Yes No Gate Level Testing OK Yes Proceed with Backend Processing ECE 448 FPGA and ASIC Design with VHDL 19 VHDL vs Verilog Government Developed Commercially Developed Ada based C based Strongly Type Cast Mildly Type Cast Difficult to learn Easy to Learn More Powerful Less Powerful ECE 448 FPGA and ASIC Design with VHDL 20 Logic Synthesis VHDL description Circuit netlist architecture MLU DATAFLOW of MLU is signal A1 STD LOGIC signal B1 STD LOGIC signal Y1 STD LOGIC signal MUX 0 MUX 1 MUX 2 MUX 3 STD LOGIC begin A1 A when NEG A 0 else not A B1 B when NEG B 0 else not B Y Y1 when NEG Y 0 else not Y1 MUX 0 A1 and B1 MUX 1 A1 or B1 MUX 2 A1 xor B1 MUX 3 A1 xnor B1 with L1 L0 select Y1 MUX 0 when 00 MUX 1 when 01 MUX 2 when 10 MUX 3 when others end MLU DATAFLOW ECE 448 FPGA and ASIC Design with VHDL 21 Logic Synthesis ECE 448 FPGA and ASIC Design with VHDL 22 TCL Tool Command Language Created by John Ousterhout of UC Berkeley Scripting Language Very simple to automate routine tasks Extension Language Used to customize tools with user company specific aplications Nearly all of modern EDA tools have a TCL interface Very simple to learn and use ECE 448 FPGA and ASIC Design with VHDL 23 TCL Example proc rfmdIfNotDirMkdir directory if file exists directory file mkdir directory if file isdirectory directory echo Could not make directory exit 1 elseif file writable directory echo directory is not writable exit 1 else return 1 ECE 448 FPGA and ASIC Design with VHDL 24 TCL References Practical Programming in Tcl and TK Brent B Welch Ken Jones TCL TK in a Nutshell Paul Raines Jeff Tranter ECE 448 FPGA and ASIC Design with VHDL 25 Basic Synthesis Flow ECE 448 FPGA and ASIC Design with VHDL 26 Synthesis using Design Compiler ECE 448 FPGA and ASIC Design with VHDL 27 ECE 448 FPGA and ASIC Design with VHDL 28 ECE 448 FPGA and ASIC Design with VHDL 29 Synthesis script 1 designer Pawel Chodowiec company George Mason University search path opt3 synopsys TSMCHOME digital Front End timing power tcb013ghp 200a link library tcb013ghptc db Typical case library target library tcb013ghptc db symbol library tcb013ghp sdb Directory configuration src directory exam1 vhdl report directory exam1 reports db directory exam1 db ECE 448 FPGA and ASIC Design with VHDL 30 Synthesis script 2 Packages can be only read read file format vhdl rtl src directory components vhd blocks regne upcount RAM 16Xn DISTRIBUTED exam1 foreach block blocks block source src directory block vhd read file format vhdl rtl block source analyze format vhdl lib WORK block source current design block All commands now apply to the entity exam1 ECE 448 FPGA and ASIC Design with VHDL 31 Synthesis script 3 uniquify Creates unique instances of multiple refrenced entities link check design Checks the current design for consistency apply block attributes and constraints create clock period 10 clk Defines that the port clk on the entity clk is the clock for the design Period 10ns 50 duty cycle Use waveform option to define duty cycle other than 50 set operating conditions NCCOM Normal Case Commercial Operating
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