ECE 448 Lecture 8 Finite State Machines State Diagrams State Tables Algorithmic State Machine ASM Charts and VHDL code ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading P Chu FPGA Prototyping by VHDL Examples Chapter 5 FSM S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 8 Synchronous Sequential Circuits Sections 8 1 8 5 Chapter 8 10 Algorithmic State Machine ASM Charts ECE 448 FPGA and ASIC Design with VHDL 2 Datapath vs Controller ECE 448 FPGA and ASIC Design with VHDL 3 Structure of a Typical Digital System Data Inputs Datapath Execution Unit Control Inputs Control Signals Controller Control Unit Status Signals Data Outputs ECE 448 FPGA and ASIC Design with VHDL Status Outputs 4 Datapath Execution Unit Manipulates and processes data Performs arithmetic and logic operations shifting and other data processing tasks Is composed of registers gates multiplexers decoders adders comparators ALUs etc Provides all necessary resources and interconnects among them to perform specified task Interprets control signals from the Controller and generates status signals for the Controller ECE 448 FPGA and ASIC Design with VHDL 5 Controller Control Unit Controls data movements in the Datapath by switching multiplexers and enabling or disabling resources Example enable signals for registers Example control signals for muxes Provides signals to activate various processing tasks in the Datapath Determines the sequence the operations performed by Datapath Follows Some Program or Schedule ECE 448 FPGA and ASIC Design with VHDL 6 Controller Controller can be programmable or non programmable Programmable Has a program counter which points to next instruction Instructions are held in a RAM or ROM externally Microprocessor is an example of programmable controller Non Programmable Once designed implements the same functionality Another term is a hardwired state machine or hardwired instructions In the following several lectures we will be focusing on non programmable controllers ECE 448 FPGA and ASIC Design with VHDL 7 Finite State Machines Digital Systems and especially their Controllers can be described as Finite State Machines FSMs Finite State Machines can be represented using State Diagrams and State Tables suitable for simple digital systems with a relatively few inputs and outputs Algorithmic State Machine ASM Charts suitable for complex digital systems with a large number of inputs and outputs All these descriptions can be easily translated to the corresponding synthesizable VHDL code ECE 448 FPGA and ASIC Design with VHDL 8 Hardware Design with RTL VHDL Interface Pseudocode Datapath Controller Block diagram VHDL code ECE 448 FPGA and ASIC Design with VHDL Block diagram VHDL code State diagram or ASM chart VHDL code 9 Finite State Machines Refresher ECE 448 FPGA and ASIC Design with VHDL 10 Finite State Machines FSMs Any Circuit with Memory Is a Finite State Machine Even computers can be viewed as huge FSMs Design of FSMs Involves Defining states Defining transitions between states Optimization minimization Manual Optimization Minimization Is Practical for Small FSMs Only ECE 448 FPGA and ASIC Design with VHDL 11 Moore FSM Output Is a Function of a Present State Only Inputs Next State function Next State clock reset Present State Present State register Output function ECE 448 FPGA and ASIC Design with VHDL Outputs 12 Mealy FSM Output Is a Function of a Present State and Inputs Inputs Next State function Next State clock reset Present State Present State register Output function ECE 448 FPGA and ASIC Design with VHDL Outputs 13 State Diagrams ECE 448 FPGA and ASIC Design with VHDL 14 Moore Machine transition condition 1 state 1 output 1 transition condition 2 ECE 448 FPGA and ASIC Design with VHDL state 2 output 2 15 Mealy Machine transition condition 1 output 1 state 2 state 1 transition condition 2 output 2 ECE 448 FPGA and ASIC Design with VHDL 16 Moore vs Mealy FSM 1 Moore and Mealy FSMs Can Be Functionally Equivalent Equivalent Mealy FSM can be derived from Moore FSM and vice versa Mealy FSM Has Richer Description and Usually Requires Smaller Number of States Smaller circuit area ECE 448 FPGA and ASIC Design with VHDL 17 Moore vs Mealy FSM 2 Mealy FSM Computes Outputs as soon as Inputs Change Mealy FSM responds one clock cycle sooner than equivalent Moore FSM Moore FSM Has No Combinational Path Between Inputs and Outputs Moore FSM is more likely to have a shorter critical path ECE 448 FPGA and ASIC Design with VHDL 18 Moore FSM Example 1 Moore FSM that Recognizes Sequence 10 0 1 S0 0 1 reset Meaning of states S0 No elements of the sequence observed ECE 448 FPGA and ASIC Design with VHDL 0 S1 0 0 S1 1 observed 1 S2 1 S2 10 observed 19 Mealy FSM Example 1 Mealy FSM that Recognizes Sequence 10 0 0 1 0 S0 reset Meaning of states 1 0 S1 0 1 S0 No elements of the sequence observed ECE 448 FPGA and ASIC Design with VHDL S1 1 observed 20 Moore Mealy FSMs Example 1 clock input Moore Mealy 0 1 0 0 S0 S1 S2 S0 S0 S0 S1 S0 S0 S0 ECE 448 FPGA and ASIC Design with VHDL 0 21 Finite State Machines in VHDL ECE 448 FPGA and ASIC Design with VHDL 22 FSMs in VHDL Finite State Machines Can Be Easily Described With Processes Synthesis Tools Understand FSM Description if Certain Rules Are Followed State transitions should be described in a process sensitive to clock and asynchronous reset signals only Output function described using rules for combinational logic i e as concurrent statements or a process with all inputs in the sensitivity list ECE 448 FPGA and ASIC Design with VHDL 23 Moore FSM process clock reset Inputs Next State function Next State clock reset Present State Register Present State Output function Outputs concurrent statements ECE 448 FPGA and ASIC Design with VHDL 24 Mealy FSM process clock reset Inputs Next State function Next State clock reset Present State Present State Register concurrent statements ECE 448 FPGA and ASIC Design with VHDL Output function Outputs 25 Moore FSM Example 1 Moore FSM that Recognizes Sequence 10 0 1 S0 0 1 0 S1 0 reset ECE 448 FPGA and ASIC Design with VHDL 1 S2 1 0 26 Moore FSM in VHDL 1 TYPE state IS S0 S1 S2 SIGNAL Moore state state U Moore PROCESS clock reset BEGIN IF reset 1 THEN Moore state S0 ELSIF clock 1 AND clock event THEN CASE Moore state IS WHEN S0 IF input 1 THEN Moore state S1 ELSE Moore state S0 END IF ECE 448 FPGA and ASIC Design with VHDL 27 Moore FSM in VHDL 2 WHEN S1 IF input 0 THEN Moore
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