ECE 448 Lecture 12 Sorting Example ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 8 10 Algorithmic State Machine ASM Charts Chapter 10 2 6 Sort Operation ECE 448 FPGA and ASIC Design with VHDL 2 Sorting ECE 448 FPGA and ASIC Design with VHDL 3 Pseudocode for the sort operation for i 0 to k 2 do A Ri for j i 1 to k 1 do B Rj if B A then Ri B Rj A A Ri end if end for end for ECE 448 FPGA and ASIC Design with VHDL 4 Structure of a Typical Digital System Data Inputs Execution Unit Datapath Control Inputs Control Signals Data Outputs ECE 448 FPGA and ASIC Design with VHDL Control Unit Control Control Outputs 5 Hardware Design with RTL VHDL Pseudocode Execution Unit Control Unit Block diagram VHDL code ECE 448 FPGA and ASIC Design with VHDL Block diagram VHDL code ASM VHDL code 6 Datapath Circuit for the sort operation DataIn ABmux n 0 n Rin0 WrInit 1 RData E Rin1 Rin2 E R0 Rin3 E E R1 R2 0 1 2 3 R3 Imux ABData Ain Bin E Rd E n Clock DataOut 1 0 Bout A B BltA ECE 448 FPGA and ASIC Design with VHDL 7 Control Circuit Part 1 0 2 2 LI L R LJ L R EI E Counter Q EJ E Counter Q Ci Cj Clock 2 2 Csel 0 1 Cmux RAdd zi k 1 zj 2 2 Int k 2 0 1 Imux 2 WrInit Wr y0 w0 w1 y 1 Rin 0 Rin 1 y2 Rin 2 y3 Rin 3 En 2 to 4 decoder ECE 448 FPGA and ASIC Design with VHDL 8 Reset S1 Ci 0 Load registers 0 s 1 S2 A Ri C j Ci ASM chart for the sort operation S3 Cj Cj 1 Ci Ci 1 S4 B Rj S5 Cj Cj 1 B A S6 1 Rj A 0 S7 Ri B S8 A Ri 0 C j k 1 S9 1 0 ECE 448 FPGA and ASIC Design with VHDL Ci k 2 Done 1 0 s 1 9 Reset S1 LI EI Int 0 0 s 1 S2 ASM chart for the Control Circuit Part 2 Int 1 Csel 0 Ain LJ EJ S3 EJ EI S4 Bin Csel 1 Int 1 S5 EJ S6 1 BltA Csel 1 Int 1 Wr Aout 0 S7 Csel 0 Int 1 Wr Bout S8 Csel 0 Int 1 Ain 0 zj S9 1 Done 0 ECE 448 FPGA and ASIC Design with VHDL zi 1 s 0 1 10 VHDL code 1 Entity declaration LIBRARY ieee USE ieee std logic 1164 all USE work components all ENTITY sort IS GENERIC N INTEGER 4 PORT Clock Resetn IN STD LOGIC s WrInit Rd IN STD LOGIC DataIn IN STD LOGIC VECTOR N 1 DOWNTO 0 RAdd IN INTEGER RANGE 0 TO 3 DataOut BUFFER STD LOGIC VECTOR N 1 DOWNTO 0 Done BUFFER STD LOGIC END sort ECE 448 FPGA and ASIC Design with VHDL 11 Package components 1 LIBRARY ieee USE ieee std logic 1164 all PACKAGE components IS n bit register with enable COMPONENT regne GENERIC N INTEGER 4 PORT R IN STD LOGIC VECTOR N 1 DOWNTO 0 Resetn IN STD LOGIC E IN STD LOGIC Clock IN STD LOGIC Q OUT STD LOGIC VECTOR N 1 DOWNTO 0 END COMPONENT ECE 448 FPGA and ASIC Design with VHDL 12 Package components 2 up counter that counts from 0 to modulus 1 COMPONENT upcount GENERIC modulus INTEGER 8 PORT Resetn IN STD LOGIC Clock IN STD LOGIC E IN STD LOGIC L IN STD LOGIC R IN INTEGER RANGE 0 TO modulus 1 Q BUFFER INTEGER RANGE 0 TO modulus 1 END COMPONENT END components ECE 448 FPGA and ASIC Design with VHDL 13 Datapath Circuit for the sort operation DataIn ABmux n 0 n Rin0 WrInit 1 RData E Rin1 Rin2 E R0 Rin3 E E R1 R2 0 1 2 3 R3 Imux ABData Ain Bin E Rd E n Clock DataOut 1 0 Bout A B BltA ECE 448 FPGA and ASIC Design with VHDL 14 VHDL code 2 Datapath signal declarations ARCHITECTURE Dataflow OF sort IS datapath data buses TYPE RegArray IS ARRAY 3 DOWNTO 0 OF STD LOGIC VECTOR N 1 DOWNTO 0 SIGNAL R RegArray SIGNAL RData STD LOGIC VECTOR N 1 DOWNTO 0 SIGNAL ABData STD LOGIC VECTOR N 1 DOWNTO 0 SIGNAL A B STD LOGIC VECTOR N 1 DOWNTO 0 SIGNAL ABMux STD LOGIC VECTOR N 1 DOWNTO 0 datapath control signals SIGNAL Rin STD LOGIC VECTOR 3 DOWNTO 0 SIGNAL IMux INTEGER RANGE 0 TO 3 SIGNAL Ain Bin STD LOGIC SIGNAL Aout Bout STD LOGIC SIGNAL BltA STD LOGIC ECE 448 FPGA and ASIC Design with VHDL 15 Control Circuit Part 1 0 2 2 LI L R LJ L R EI E Counter Q EJ E Counter Q Ci Cj Clock 2 2 Csel 0 1 Cmux RAdd zi k 1 zj 2 2 Int k 2 0 1 Imux 2 WrInit Wr y0 w0 w1 y 1 Rin 0 Rin 1 y2 Rin 2 y3 Rin 3 En 2 to 4 decoder ECE 448 FPGA and ASIC Design with VHDL 16 VHDL code 3 Control unit signal declarations control unit Part 1 SIGNAL Zero SIGNAL Ci Cj SIGNAL CMux INTEGER RANGE 3 DOWNTO 0 INTEGER RANGE 0 TO 3 INTEGER RANGE 0 TO 3 SIGNAL LI LJ SIGNAL EI EJ STD LOGIC STD LOGIC SIGNAL zi zj SIGNAL Csel SIGNAL Int SIGNAL Wr STD LOGIC STD LOGIC STD LOGIC STD LOGIC control unit Part 2 TYPE State type IS S1 S2 S3 S4 S5 S6 S7 S8 S9 SIGNAL y State type ECE 448 FPGA and ASIC Design with VHDL 17 Datapath Circuit for the sort operation DataIn ABmux n 0 n Rin0 WrInit 1 RData E Rin1 Rin2 E R0 Rin3 E E R1 R2 0 1 2 3 R3 Imux ABData Ain Bin E Rd E n Clock DataOut 1 0 Bout A B BltA ECE 448 FPGA and ASIC Design with VHDL 18 VHDL code 4 Datapath BEGIN RData ABMux WHEN WrInit 0 ELSE DataIn GenReg FOR i IN 0 TO 3 GENERATE Reg regne GENERIC MAP N N PORT MAP R RData Resetn Resetn E Rin i Clock Clock Q R i END GENERATE WITH IMux Select ABData R 0 WHEN 0 R 1 WHEN 1 R 2 WHEN 2 R 3 WHEN OTHERS ECE 448 FPGA and ASIC Design with VHDL 19 VHDL code 5 Datapath RegA regne GENERIC MAP N N PORT MAP R ABData Resetn Resetn E Ain Clock Clock Q A RegB regne GENERIC MAP N N PORT MAP R ABData Resetn Resetn E Bin Clock Clock Q B BltA 1 WHEN B A ELSE 0 ABMux A WHEN Bout 0 ELSE B DataOut OTHERS Z WHEN Rd 0 ELSE ABData ECE 448 FPGA and ASIC Design with VHDL 20 Control Circuit Part 1 0 2 2 LI L R …
View Full Document
Unlocking...