ECE 448 Lab 1 Developing Effective Testbenches ECE 448 FPGA and ASIC Design with VHDL George Mason University Agenda for today Part 1 Introduction General Lab Rules Part 2 Refresher on VHDL Testbenches Part 3 Introduction to Lab 1 Developing Effective Testbenches Part 4 Hands on Session Simulation using Aldec Active HDL 2 Part 1 Introduction General Lab Rules ECE 448 FPGA and ASIC Design with VHDL 3 See the Rules posted at the Course Web Page Follow this link 4 Part 2 Refresher on VHDL Testbenches ECE 448 FPGA and ASIC Design with VHDL 5 Testbench Defined Testbench VHDL entity that applies stimuli drives the inputs to the Design Under Test DUT and optionally verifies expected outputs The results can be viewed in a waveform window or written to a file Since Testbench is written in VHDL it is not restricted to a single simulation tool portability The same Testbench can be easily adapted to test different implementations i e different architectures of the same design ECE 448 FPGA and ASIC Design with VHDL 6 Simple Testbench Processes Generating Design Under Test DUT Stimuli Observed Outputs ECE 448 FPGA and ASIC Design with VHDL 7 Possible sources of expected results used for comparison Testbench VHDL Design actual results Representative Manual Calculations Inputs or expected results Reference Software Implementation C Java Matlab ECE 448 FPGA and ASIC Design with VHDL 8 Test vectors Set of pairs Input i Expected Output i Input 1 Expected Output 1 Input 2 Expected Output 2 Input N Expected Output N Test vectors can cover either all combinations of inputs for very simple circuits only selected representative combinations of inputs most realistic circuits ECE 448 FPGA and ASIC Design with VHDL 9 Testbench The same testbench can be used to test multiple implementations of the same circuit multiple architectures testbench design entity Architecture 1 Architecture 2 ECE 448 FPGA and ASIC Design with VHDL Architecture N 10 Testbench Anatomy ENTITY my entity tb IS TB entity has no ports END my entity tb ARCHITECTURE behavioral OF tb IS Local signals and constants COMPONENT TestComp All Design Under Test component declarations PORT END COMPONENT BEGIN DUT TestComp PORT MAP Instantiations of DUTs testSequence PROCESS Input stimuli END PROCESS END behavioral ECE 448 FPGA and ASIC Design with VHDL 11 Testbench for XOR3 1 LIBRARY ieee USE ieee std logic 1164 all ENTITY xor3 tb IS END xor3 tb ARCHITECTURE behavioral OF xor3 tb IS Component declaration of the tested unit COMPONENT xor3 PORT A IN STD LOGIC B IN STD LOGIC C IN STD LOGIC Result OUT STD LOGIC END COMPONENT Stimulus signals signals mapped to the input and inout ports of tested entity SIGNAL test vector STD LOGIC VECTOR 2 DOWNTO 0 SIGNAL test result STD LOGIC ECE 448 FPGA and ASIC Design with VHDL 12 Testbench for XOR3 2 BEGIN UUT xor3 PORT MAP A test vector 2 B test vector 1 C test vector 0 Result test result Testing PROCESS BEGIN test vector 000 WAIT FOR 10 ns test vector 001 WAIT FOR 10 ns test vector 010 WAIT FOR 10 ns test vector 011 WAIT FOR 10 ns test vector 100 WAIT FOR 10 ns test vector 101 WAIT FOR 10 ns test vector 110 WAIT FOR 10 ns test vector 111 WAIT FOR 10 ns END PROCESS END behavioral ECE 448 FPGA and ASIC Design with VHDL 13 VHDL Design Styles VHDL Design Styles dataflow Concurrent statements structural Components and interconnects ECE 448 FPGA and ASIC Design with VHDL behavioral Sequential statements Testbenches 14 Process without Sensitivity List and its use in Testbenches ECE 448 FPGA and ASIC Design with VHDL 15 What is a PROCESS A process is a sequence of instructions referred to as sequential statements The keyword PROCESS A process can be given a unique name using an optional LABEL This is followed by the keyword PROCESS The keyword BEGIN is used to indicate the start of the process All statements within the process are executed SEQUENTIALLY Hence order of statements is important Testing PROCESS BEGIN test vector 00 WAIT FOR 10 ns test vector 01 WAIT FOR 10 ns test vector 10 WAIT FOR 10 ns test vector 11 WAIT FOR 10 ns END PROCESS A process must end with the keywords END PROCESS ECE 448 FPGA and ASIC Design with VHDL 16 Execution of statements in a PROCESS The execution of statements continues sequentially till the last statement in the process After execution of the last statement the control is again passed to the beginning of the process Order of execution Testing PROCESS BEGIN test vector 00 WAIT FOR 10 ns test vector 01 WAIT FOR 10 ns test vector 10 WAIT FOR 10 ns test vector 11 WAIT FOR 10 ns END PROCESS Program control is passed to the first statement after BEGIN ECE 448 FPGA and ASIC Design with VHDL 17 PROCESS with a WAIT Statement The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non periodical signal has to be generated Testing PROCESS BEGIN test vector 00 WAIT FOR 10 ns test vector 01 WAIT FOR 10 ns test vector 10 WAIT FOR 10 ns test vector 11 WAIT END PROCESS Order of execution Program execution stops here ECE 448 FPGA and ASIC Design with VHDL 18 WAIT FOR vs WAIT WAIT FOR waveform will keep repeating itself forever 0 1 2 3 0 1 2 3 WAIT waveform will keep its state after the last wait instruction ECE 448 FPGA and ASIC Design with VHDL 19 Specifying time in VHDL ECE 448 FPGA and ASIC Design with VHDL 20 Time values physical literals Examples 7 ns 1 min min 10 65 us 10 65 fs Numeric value ECE 448 FPGA and ASIC Design with VHDL unit of time most commonly used in simulation Space Unit of time required 21 Units of time Unit Base Unit fs Derived Units ps ns us ms sec min hr Definition femtoseconds 10 15 seconds picoseconds 10 12 seconds nanoseconds 10 9 seconds microseconds 10 6 seconds miliseconds 10 3 seconds seconds minutes 60 seconds hours 3600 seconds ECE 448 FPGA and ASIC Design with VHDL 22 Simple Testbenches ECE 448 FPGA and ASIC Design with VHDL 23 Generating selected values of one input SIGNAL test vector STD LOGIC VECTOR 2 downto 0 BEGIN testing PROCESS BEGIN test vector 000 WAIT FOR 10 ns test vector 001 WAIT FOR 10 ns test vector 010 WAIT FOR 10 ns test vector 011 WAIT FOR 10 ns test vector 100 WAIT FOR 10 ns END PROCESS END behavioral ECE 448 FPGA and ASIC Design with VHDL 24 Generating all values of one input USE ieee std logic unsigned all SIGNAL test
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