Lecture 2 VHDL Refresher ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 2 9 Introduction to CAD tools Chapter 2 10 Introduction to VHDL Chapter 4 12 Examples of Circuits Synthesized from VHDL Code Chapter 5 5 3 Representation of Numbers in VHDL Code ECE 448 FPGA and ASIC Design with VHDL 2 Recommended reading Sundar Rajan Essential VHDL RTL Synthesis Done Right Chapter 1 VHDL Fundamentals Chapter 2 Getting Your First Design Done see errata at http www vahana com bugs htm ECE 448 FPGA and ASIC Design with VHDL 3 Recommended reading Wikipedia The Free On line Encyclopedia VHDL http en wikipedia org wiki VHDL Verilog http en wikipedia org wiki Verilog ECE 448 FPGA and ASIC Design with VHDL 4 Recommended reading for next week Material covered next week and required during the first lab experiment S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 6 Combinational Circuit Building Blocks Chapter 5 5 Design of Arithmetic Circuits Using CAD Tools ECE 448 FPGA and ASIC Design with VHDL 5 Brief History of VHDL ECE 448 FPGA and ASIC Design with VHDL 6 VHDL VHDL is a language for describing digital hardware used by industry worldwide VHDL is an acronym for VHSIC Very High Speed Integrated Circuit Hardware Description Language ECE 448 FPGA and ASIC Design with VHDL 7 Genesis of VHDL State of art circa 1980 Multiple design entry methods and hardware description languages in use No or limited portability of designs between CAD tools from different vendors Objective shortening the time from a design concept to implementation from 18 months to 6 months ECE 448 FPGA and ASIC Design with VHDL 8 A Brief History of VHDL June 1981 Woods Hole Workshop July 1983 contract awarded to develop VHDL Intermetrics IBM Texas Instruments August 1985 VHDL Version 7 2 released December 1987 VHDL became IEEE Standard 1076 1987 and in 1988 an ANSI standard ECE 448 FPGA and ASIC Design with VHDL 9 Three versions of VHDL VHDL 87 VHDL 93 VHDL 01 VHDL 06 ECE 448 FPGA and ASIC Design with VHDL 10 Verilog ECE 448 FPGA and ASIC Design with VHDL 11 Verilog Essentially identical in function to VHDL No generate statement Simpler and syntactically different C like Gateway Design Automation Co 1985 Gateway acquired by Cadence in 1990 IEEE Standard 1364 1995 Early de facto standard for ASIC programming Programming language interface to allow connection to non Verilog code ECE 448 FPGA and ASIC Design with VHDL 12 VHDL vs Verilog Government Developed Commercially Developed Ada based C based Strongly Type Cast Mildly Type Cast Case insensitive Case sensitive Difficult to learn Easier to Learn More Powerful Less Powerful ECE 448 FPGA and ASIC Design with VHDL 13 How to learn Verilog by yourself ECE 448 FPGA and ASIC Design with VHDL 14 Features of VHDL and Verilog Technology vendor independent Portable Reusable ECE 448 FPGA and ASIC Design with VHDL 15 VHDL for Synthesis ECE 448 FPGA and ASIC Design with VHDL 16 VHDL for Specification VHDL for Simulation VHDL for Synthesis ECE 448 FPGA and ASIC Design with VHDL 17 Levels of design description Algorithmic level Register Transfer Level Level of description most suitable for synthesis Logic gate level Circuit transistor level Physical layout level ECE 448 FPGA and ASIC Design with VHDL 18 Register Transfer Level RTL Design Description Combinational Logic Combinational Logic Registers ECE 448 FPGA and ASIC Design with VHDL 19 VHDL Fundamentals ECE 448 FPGA and ASIC Design with VHDL 20 Naming and Labeling 1 VHDL is case insensitive Example Names or labels databus Databus DataBus DATABUS are all equivalent ECE 448 FPGA and ASIC Design with VHDL 21 Naming and Labeling 2 General rules of thumb according to VHDL 87 1 2 3 4 5 All names should start with an alphabet character a z or A Z Use only alphabet characters a z or A Z digits 0 9 and underscore Do not use any punctuation or reserved characters within a name etc Do not use two or more consecutive underscore characters within a name e g Sel A is invalid All names and labels in a given entity and architecture must be unique ECE 448 FPGA and ASIC Design with VHDL 22 Valid or invalid 7segment display A87372477424 Adder Subtractor reset And or gate AND OR NOT Kogge Stone Adder Ripple Carry Adder My adder ECE 448 FPGA and ASIC Design with VHDL 23 Free Format VHDL is a free format language No formatting conventions such as spacing or indentation imposed by VHDL compilers Space and carriage return treated the same way Example if a b then or if a b then or if a b then are all equivalent ECE 448 FPGA and ASIC Design with VHDL 24 Readability standards ESA VHDL Modelling Guidelines published by European Space Research and Technology Center in September 1994 available at the course web page ECE 448 FPGA and ASIC Design with VHDL 25 Comments Comments in VHDL are indicated with a double dash i e Comment indicator can be placed anywhere in the line Any text that follows in the same line is treated as a comment Carriage return terminates a comment No method for commenting a block extending over a couple of lines Examples main subcircuit Data in Data bus reading data from the input FIFO ECE 448 FPGA and ASIC Design with VHDL 26 Comments Explain Function of Module to Other Designers Explanatory Not Just Restatement of Code Locate Close to Code Described Put near executable code not just in a header ECE 448 FPGA and ASIC Design with VHDL 27 Design Entity ECE 448 FPGA and ASIC Design with VHDL 28 Design Entity design entity entity declaration Design Entity most basic building block of a design architecture 1 architecture 2 One entity can have many different architectures architecture 3 ECE 448 FPGA and ASIC Design with VHDL 29 Entity Declaration Entity Declaration describes the interface of the component i e input and output ports Entity name Port names Port type ENTITY nand gate IS PORT a IN STD LOGIC b IN STD LOGIC z OUT STD LOGIC END nand gate Reserved words Semicolon No Semicolon Port modes data flow directions ECE 448 FPGA and ASIC Design with VHDL 30 Entity declaration simplified syntax ENTITY entity name IS PORT port name signal mode signal type port name signal mode signal type port name signal mode signal type END entity name ECE 448 FPGA and ASIC Design with VHDL 31 Architecture Describes an implementation of a design entity Architecture example ARCHITECTURE model OF nand gate IS BEGIN z a NAND b END model ECE
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