ECE 448 Lecture 9 Modeling of Circuits with a Regular Structure Aliases Constants Packages Mixing Design Styles ECE 448 FPGA and ASIC Design with VHDL George Mason University Required reading S Brown and Z Vranesic Fundamentals of Digital Logic with VHDL Design Chapter 6 6 4 Generate Statements Chapter A 7 5 Generate Statement Chapter A 10 9 Using Subcircuits with Generic Parameters Chapter A 11 Common Errors in VHDL Code P Chu FPGA Prototyping by VHDL Examples Chapter 3 6 Constants and Generics ECE 448 FPGA and ASIC Design with VHDL 2 Generate scheme for equations ECE 448 FPGA and ASIC Design with VHDL 3 Data flow VHDL Major instructions Concurrent statements concurrent signal assignment conditional concurrent signal assignment when else selected concurrent signal assignment with select when generate scheme for equations for generate ECE 448 FPGA and ASIC Design with VHDL 4 PARITY Example ECE 448 FPGA and ASIC Design with VHDL 5 PARITY Block Diagram ECE 448 FPGA and ASIC Design with VHDL 6 PARITY Entity Declaration LIBRARY ieee USE ieee std logic 1164 all ENTITY parity IS PORT parity in IN STD LOGIC VECTOR 7 DOWNTO 0 parity out OUT STD LOGIC END parity ECE 448 FPGA and ASIC Design with VHDL 7 PARITY Block Diagram xor out 1 xor out 2 xor out 3 ECE 448 FPGA and ASIC Design with VHDL xor out 4 xor out 5 xor out 6 8 PARITY Architecture ARCHITECTURE parity dataflow OF parity IS SIGNAL xor out std logic vector 6 downto 1 BEGIN xor out 1 parity in 0 XOR parity in 1 xor out 2 xor out 1 XOR parity in 2 xor out 3 xor out 2 XOR parity in 3 xor out 4 xor out 3 XOR parity in 4 xor out 5 xor out 4 XOR parity in 5 xor out 6 xor out 5 XOR parity in 6 parity out xor out 6 XOR parity in 7 END parity dataflow ECE 448 FPGA and ASIC Design with VHDL 9 PARITY Block Diagram 2 xor out 0 xor out 1 xor out 2 xor out 3 ECE 448 FPGA and ASIC Design with VHDL xor out 4 xor out 5 xor out 6 xor out 7 10 PARITY Architecture ARCHITECTURE parity dataflow OF parity IS SIGNAL xor out STD LOGIC VECTOR 7 downto 0 BEGIN xor out 0 parity in 0 xor out 1 xor out 0 XOR parity in 1 xor out 2 xor out 1 XOR parity in 2 xor out 3 xor out 2 XOR parity in 3 xor out 4 xor out 3 XOR parity in 4 xor out 5 xor out 4 XOR parity in 5 xor out 6 xor out 5 XOR parity in 6 xor out 7 xor out 6 XOR parity in 7 parity out xor out 7 END parity dataflow ECE 448 FPGA and ASIC Design with VHDL 11 PARITY Architecture 2 ARCHITECTURE parity dataflow OF parity IS SIGNAL xor out STD LOGIC VECTOR 7 DOWNTO 0 BEGIN xor out 0 parity in 0 G2 FOR i IN 1 TO 7 GENERATE xor out i xor out i 1 XOR parity in i END GENERATE G2 parity out xor out 7 END parity dataflow ECE 448 FPGA and ASIC Design with VHDL 12 For Generate Statement For Generate label FOR identifier IN range GENERATE BEGIN Concurrent Statements END GENERATE ECE 448 FPGA and ASIC Design with VHDL 13 Generate scheme for components ECE 448 FPGA and ASIC Design with VHDL 14 Structural VHDL Major instructions component instantiation port map component instantiation with generic generic map port map generate scheme for component instantiations for generate ECE 448 FPGA and ASIC Design with VHDL 15 Example 1 ECE 448 FPGA and ASIC Design with VHDL 16 Example 1 s0 s1 w0 w3 w4 s2 s3 w7 f w8 w11 w12 w15 ECE 448 FPGA and ASIC Design with VHDL 17 A 4 to 1 Multiplexer LIBRARY ieee USE ieee std logic 1164 all ENTITY mux4to1 IS PORT w0 w1 w2 w3 s IN f OUT END mux4to1 IN STD LOGIC STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC ARCHITECTURE Dataflow OF mux4to1 IS BEGIN WITH s SELECT f w0 WHEN 00 w1 WHEN 01 w2 WHEN 10 w3 WHEN OTHERS END Dataflow ECE 448 FPGA and ASIC Design with VHDL 18 Straightforward code for Example 1 LIBRARY ieee USE ieee std logic 1164 all ENTITY Example1 IS PORT w IN s IN f OUT END Example1 STD LOGIC VECTOR 0 TO 15 STD LOGIC VECTOR 3 DOWNTO 0 STD LOGIC ECE 448 FPGA and ASIC Design with VHDL 19 Straightforward code for Example 1 ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT w0 w1 w2 w3 IN STD LOGIC s IN STD LOGIC VECTOR 1 DOWNTO 0 f OUT STD LOGIC END COMPONENT SIGNAL m STD LOGIC VECTOR 0 TO 3 BEGIN Mux1 mux4to1 PORT MAP w 0 Mux2 mux4to1 PORT MAP w 4 Mux3 mux4to1 PORT MAP w 8 Mux4 mux4to1 PORT MAP w 12 Mux5 mux4to1 PORT MAP m 0 END Structure w 1 w 5 w 9 w 13 m 1 ECE 448 FPGA and ASIC Design with VHDL w 2 w 6 w 10 w 14 m 2 w 3 w 7 w 11 w 15 m 3 s 1 DOWNTO 0 m 0 s 1 DOWNTO 0 m 1 s 1 DOWNTO 0 m 2 s 1 DOWNTO 0 m 3 s 3 DOWNTO 2 f 20 Modified code for Example 1 ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT w0 w1 w2 w3 s f END COMPONENT IN IN OUT STD LOGIC STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC SIGNAL m STD LOGIC VECTOR 0 TO 3 BEGIN G1 FOR i IN 0 TO 3 GENERATE Muxes mux4to1 PORT MAP w 4 i w 4 i 1 w 4 i 2 w 4 i 3 s 1 DOWNTO 0 m i END GENERATE Mux5 mux4to1 PORT MAP m 0 m 1 m 2 m 3 s 3 DOWNTO 2 f END Structure ECE 448 FPGA and ASIC Design with VHDL 21 Example 2 ECE 448 FPGA and ASIC Design with VHDL 22 Example 2 w1 w0 w1 w0 En w1 w0 w3 w2 w1 w0 En En y3 y2 y1 y0 En w1 w0 En w1 w0 En ECE 448 FPGA and ASIC Design with VHDL y3 y2 y1 y0 y15 y14 y13 y12 y3 y2 y1 y0 y11 y10 y9 y8 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 y0 y3 y2 y1 y0 23 A 2 to 4 binary decoder LIBRARY ieee USE ieee std logic 1164 all ENTITY dec2to4 IS PORT w IN En IN y OUT END dec2to4 STD LOGIC VECTOR 1 DOWNTO 0 STD LOGIC STD LOGIC VECTOR 3 DOWNTO 0 ARCHITECTURE Dataflow OF dec2to4 IS SIGNAL Enw STD LOGIC VECTOR 2 DOWNTO 0 BEGIN Enw En w WITH Enw SELECT y 0001 WHEN 100 0010 WHEN 101 0100 WHEN 110 1000 WHEN 111 0000 WHEN OTHERS END Dataflow ECE 448 FPGA and ASIC Design with VHDL 24 VHDL code for Example 2 1 LIBRARY ieee USE ieee std logic 1164 all …
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